Patents by Inventor Tsong-Hua Ou
Tsong-Hua Ou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9287125Abstract: Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.Type: GrantFiled: May 19, 2014Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Ya Hui Chang, Ru-Gun Liu, Tsong-Hua Ou, Ken-Hsien Hsieh, Burn Jeng Lin
-
Patent number: 9281273Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: 0.2 ? ? P gate ? ? min + 0.35 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min - 20 0.2 ? ? L gate ? ? min + 0.8 ? ? H gate ? ? min - 5 × 0.3 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min + 5 38 ? 0.32 Pgate min is the minimum value among gate pitches of the gate structures.Type: GrantFiled: September 3, 2014Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Co., LTD.Inventors: Chih-Liang Chen, Chih-Ming Lai, Yung-Sung Yen, Kam-Tou Sio, Tsong-Hua Ou, Chun-Kuang Chen, Ru-Gun Liu, Shu-Hui Sung, Charles Chew-Yuen Young
-
Publication number: 20160064322Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: 0.2 ? ? P gate ? ? min + 0.35 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min - 20 0.2 ? ? L gate ? ? min + 0.8 ? ? H gate ? ? min - 5 × 0.3 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min + 5 38 ? 0.32 Pgate min is the minimum value among gate pitches of the gate structures.Type: ApplicationFiled: September 3, 2014Publication date: March 3, 2016Inventors: Chih-Liang CHEN, Chih-Ming LAI, Yung-Sung YEN, Kam-Tou SIO, Tsong-Hua OU, Chun-Kuang CHEN, Ru-Gun LIU, Shu-Hui SUNG, Charles Chew-Yuen YOUNG
-
Patent number: 9262577Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.Type: GrantFiled: May 1, 2014Date of Patent: February 16, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Tsong-Hua Ou, Ken-Hsien Hsieh, Chin-Hsiung Hsu
-
Publication number: 20160019333Abstract: A method of determining whether a layout is colorable includes assigning nodes to polygon features of the layout. The method includes designating nodes as being adjacent nodes for nodes separated by less than a minimum pitch. The method includes iteratively removing nodes having less than three adjacent nodes from consideration to identify a node arrangement, wherein all nodes in the node arrangement have at least three adjacent nodes. The method includes determining whether the layout is colorable based on the node arrangement. Determining whether the layout is colorable includes independently assessing each internal node of node arrangement to determine whether each internal node of the node arrangement is colorable. The method includes generating a colored layout design for fabrication of the semiconductor device if each internal node of the node arrangement is colorable; and modifying the layout if at least one internal node of the node arrangement is not colorable.Type: ApplicationFiled: October 1, 2015Publication date: January 21, 2016Inventors: Wen-Li CHENG, Ming-Hui CHIH, Chia-Ping CHIANG, Ken-Hsien HSIEH, Tsong-Hua OU, Wen-Chun HUANG, Ru-Gun LIU
-
Patent number: 9176373Abstract: A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain, identify one or more internal nodes, map photoresist mask pattern designations (colors) to the internal nodes, and replace and map a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color.Type: GrantFiled: July 31, 2013Date of Patent: November 3, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Li Cheng, Ming-Hui Chih, Chia-Ping Chiang, Ken-Hsien Hsieh, Tsong-Hua Ou, Wen-Chun Huang, Ru-Gun Liu
-
Publication number: 20150311063Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of: forming a plurality of first features over the target material layer using a first sub-layout, with each first feature having sidewalls; forming a plurality of spacer features, with each spacer feature conforming to the sidewalls of one of the first features and having a spacer width; and forming a plurality of second features over the target material layer using a second sub-layout. The method further includes steps of removing the plurality of spacer features from around each first feature and patterning the target material layer using the plurality of first features and the plurality of second features. Other methods and associated patterned semiconductor wafers are also provided herein.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
-
Patent number: 9026971Abstract: The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.Type: GrantFiled: January 7, 2014Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien Lin Ho, Chin-Chang Hsu, Hung Lung Lin, Wen-Ju Yang, Yi-Kan Cheng, Tsong-Hua Ou, Wen-Li Cheng, Ken-Hsien Hsieh, Ching Hsiang Chang, Ting Yu Chen, Li-Chun Tien
-
Patent number: 9026957Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.Type: GrantFiled: February 25, 2014Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
-
Publication number: 20150040083Abstract: A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain, identify one or more internal nodes, map photoresist mask pattern designations (colors) to the internal nodes, and replace and map a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Li CHENG, Ming-Hui CHIH, Chia-Ping CHIANG, Ken-Hsien HSIEH, Tsong-Hua OU, Wen-Chun HUANG, Ru-Gun LIU
-
Patent number: 8907497Abstract: A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.Type: GrantFiled: April 27, 2012Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou
-
Publication number: 20140259658Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.Type: ApplicationFiled: June 24, 2013Publication date: September 18, 2014Inventors: Chin-Hsiung HSU, Huang-Yu CHEN, Tsong-Hua OU, Wen-Hao CHEN
-
Publication number: 20140252559Abstract: Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.Type: ApplicationFiled: May 19, 2014Publication date: September 11, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, YA HUI CHANG, RU-GUN LlU, TSONG-HUA OU, KEN-HSIEN HSIEH, BURN JENG LIN
-
Publication number: 20140237435Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.Type: ApplicationFiled: May 1, 2014Publication date: August 21, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu CHEN, Tsong-Hua OU, Ken-Hsien HSIEH, Chin-Hsiung HSU
-
Patent number: 8806392Abstract: A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.Type: GrantFiled: December 3, 2012Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Tzu-Chin Lin, Jen-Chieh Lo, Yu-Po Tang, Tsong-Hua Ou
-
Patent number: 8806386Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.Type: GrantFiled: November 25, 2009Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Chou Cheng, Ru-Gun Liu, Josh J. H. Feng, Tsong-Hua Ou, Luke Lo, Chih-Ming Lai, Wen-Chun Huang
-
Publication number: 20140203378Abstract: A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.Type: ApplicationFiled: March 20, 2014Publication date: July 24, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsong-Hua Ou, Shu-Min Chen, Pin-Dai Sue, Li-Chun Tien, Ru-Gun Liu
-
Publication number: 20140170537Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.Type: ApplicationFiled: February 25, 2014Publication date: June 19, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
-
Publication number: 20140157212Abstract: A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.Type: ApplicationFiled: December 3, 2012Publication date: June 5, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Tzu-Chin Lin, Jen-Chieh Lo, Yu-Po Tang, Tsong-Hua Ou
-
Patent number: 8745556Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.Type: GrantFiled: June 28, 2012Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Tsong-Hua Ou, Ken-Hsien Hsieh, Chin-Hsiung Hsu