Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

Abstract: A method includes: etching a trench on a surface of a substrate; filling the trench with a dielectric material to form a first isolation region; depositing a patterned mask layer on the substrate, the patterned mask layer comprising an opening exposing the substrate; implanting oxygen into the substrate through the opening to form an implant region; generating a second isolation region from the implant region; and forming a transistor on the substrate. The transistor includes a channel laterally surrounding the second isolation region.

Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.

Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.

Abstract: The present disclosure provides an interconnect structure, including a substrate having a conductive region adjacent to a gate region, a contact over the conductive region, a first interlayer dielectric layer (ILD) surrounding the contact, a via over the contact, a first densified dielectric layer surrounding the via, wherein the densified dielectric layer has a first density, and a second ILD layer over the first ILD layer and surrounding the via, wherein the second ILD layer has a second density, the first density is greater than a second density.

Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.