Patents by Inventor Tsukasa Ooishi

Tsukasa Ooishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7719814
    Abstract: A semiconductor device includes a memory cell to and from which data is written and read in accordance with voltage supplied, a power supply circuit generating the voltage supplied to the memory cell, a microcomputer, an external terminal, a surge protection circuit clamping at a predetermined voltage value a voltage supplied to the external terminal, and a first switch circuit switching to output to one of the power supply circuit and the microcomputer a voltage having passed through the surge protection circuit. The power supply circuit includes a voltage conversion circuit changing the magnitude of a voltage received from the first switch circuit, and a second switch circuit switching to supply the memory cell with one of the voltage received from the first switch circuit and the voltage changed in magnitude.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: May 18, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Mutsuo Kobayashi, Tsukasa Ooishi
  • Patent number: 7672173
    Abstract: For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are reset to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: March 2, 2010
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Tsukasa Ooishi, Tomohiro Uchiyama, Shinya Miyazaki
  • Patent number: 7552378
    Abstract: In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from an L level identified as a reset state is increased than the case where the drivability is set equal. Thus, the time required to output a syndrome from a plurality of stages of XOR gates can be reduced to allow execution of error correction processing at high speed.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: June 23, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Tomoya Kawagoe, Tsukasa Ooishi
  • Publication number: 20080239795
    Abstract: A data write current from a pinned layer to a free layer is larger than a data write current from the free layer to the pinned layer. A data read current is smaller in value than the data write current. In the case where a difference in data read current between a high-resistance state and a low-resistance state is relatively small, a sense amplifier is connected so that the data read current flows from the pinned layer to the free layer, namely from a source line to a bit line.
    Type: Application
    Filed: June 5, 2008
    Publication date: October 2, 2008
    Applicant: RENESAS TECHNOLOGY CORP
    Inventors: Tsukasa OOISHI, Hideto Hidaka
  • Patent number: 7394685
    Abstract: A data write current from a pinned layer to a free layer is larger than a data write current from the free layer to the pinned layer. A data read current is smaller in value than the data write current. In the case where a difference in data read current between a high-resistance state and a low-resistance state is relatively small, a sense amplifier is connected so that the data read current flows from the pinned layer to the free layer, namely from a source line to a bit line.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: July 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Tsukasa Ooishi, Hideto Hidaka
  • Publication number: 20080048767
    Abstract: A semiconductor device includes a memory cell to and from which data is written and read in accordance with voltage supplied, a power supply circuit generating the voltage supplied to the memory cell, a microcomputer, an external terminal, a surge protection circuit clamping at a predetermined voltage value a voltage supplied to the external terminal, and a first switch circuit switching to output to one of the power supply circuit and the microcomputer a voltage having passed through the surge protection circuit. The power supply circuit includes a voltage conversion circuit changing the magnitude of a voltage received from the first switch circuit, and a second switch circuit switching to supply the memory cell with one of the voltage received from the first switch circuit and the voltage changed in magnitude.
    Type: Application
    Filed: July 12, 2007
    Publication date: February 28, 2008
    Inventors: Mutsuo Kobayashi, Tsukasa Ooishi
  • Patent number: 7336529
    Abstract: Each of program cell and memory cells includes a magnetic storage portion of the same configuration. The program cell further includes a state change portion. That is, the program cell has the same structure as the memory cell, except that the state change portion is additionally provided thereto. As such, the program cell can be provided efficiently, as it can be designed the same as the memory cell in terms of the magnetic storage portion and others. The state change portion makes a transition to a fixed state based on an electrical change. Thus, the state change portion prevents program information from being rewritten by a magnetic noise or the like, and ensures stable storage of the program information.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: February 26, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Tsukasa Ooishi
  • Publication number: 20080019195
    Abstract: For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.
    Type: Application
    Filed: September 20, 2007
    Publication date: January 24, 2008
    Applicants: RENESAS TECHNOLOGY CORP., HITACHI ULSI SYSTEMS CO., LTD.
    Inventors: Tsukasa OOISHI, Tomohiro UCHIYAMA, Shinya MIYAZAKI
  • Publication number: 20080013358
    Abstract: A write bit line and a read bit line are provided separately for a memory cell. A source line connecting to the memory cell is formed of a source impurity region the same in conductivity type as a substrate region. A memory cell transistor and the source impurity region are connected by a metal interconnection line of a low resistance. A rise in the source line potential can be prevented, and a memory cell current can reliably be generated according to storage data. Further, fast data reading can be achieved. Additionally, by performing precharging and data amplification in a unit of read bit line, the load of the read bit line can be alleviated to achieve fast reading. An accessing time of a non-volatile semiconductor memory device that uses a variable resistance element as a storage element is reduced without increasing the current consumption.
    Type: Application
    Filed: September 12, 2007
    Publication date: January 17, 2008
    Applicant: Renesas Technology Corp.
    Inventor: Tsukasa Ooishi
  • Patent number: 7313017
    Abstract: In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: December 25, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tsukasa Ooishi, Hideto Hidaka
  • Patent number: 7313014
    Abstract: Shape dummy cells that are designed to have the same dimensions and structures as MTJ memory cells are additionally provided in the peripheral portion of an MTJ memory cell array in which normal MTJ memory cells for storing data are arranged in a matrix. The MTJ memory cells and the shape dummy cells are sequentially arranged so as to have a uniform pitch throughout the entirety. Accordingly, non-uniformity between MTJ memory cells in the center portion and in border portions of the MTJ memory cell array, respectively, after manufacture due to high and low densities of the surrounding memory cells can be eliminated.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: December 25, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Tsukasa Ooishi
  • Patent number: 7295465
    Abstract: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: November 13, 2007
    Assignees: Renesas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventors: Hiroaki Tanizaki, Hideto Hidaka, Tsukasa Ooishi
  • Patent number: 7286416
    Abstract: For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: October 23, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Tsukasa Ooishi, Tomohiro Uchiyama, Shinya Miyazaki
  • Patent number: 7286394
    Abstract: A write bit line and a read bit line are provided separately for a memory cell. A source line connecting to the memory cell is formed of a source impurity region the same in conductivity type as a substrate region. A memory cell transistor and the source impurity region are connected by a metal interconnection line of a low resistance. A rise in the source line potential can be prevented, and a memory cell current can reliably be generated according to storage data. Further, fast data reading can be achieved. Additionally, by performing precharging and data amplification in a unit of read bit line, the load of the read bit line can be alleviated to achieve fast reading. An accessing time of a non-volatile semiconductor memory device that uses a variable resistance element as a storage element is reduced without increasing the current consumption.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: October 23, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Tsukasa Ooishi
  • Patent number: 7277330
    Abstract: In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the two spare memory cells and connecting these spare memory cells to a sense amplifier, the stored data of one bit is read. A spare memory cell section which is often arranged in an array peripheral portion becomes more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell increases.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: October 2, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Tsukasa Ooishi
  • Patent number: 7272064
    Abstract: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: September 18, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Tsukasa Ooishi
  • Patent number: 7256644
    Abstract: Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: August 14, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tsukasa Ooishi, Hideto Hidaka
  • Publication number: 20070158634
    Abstract: Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row select signal. Corresponding to a row of memory cells, there is provided a word line connecting to memory cells on corresponding row and transmitting the row select signal, and a word line shunting line electrically connected at predetermined intervals to each word line. Moreover, corresponding to a row of dummy cells and a column of dummy cells, there is provided substrate shunt lines electrically connected to the substrate region. The voltage distribution in the substrate region is eliminated to achieve stable operating characteristics of the memory cell transistor. In addition, a word line is driven at high speed by a word line shunt structure.
    Type: Application
    Filed: March 9, 2007
    Publication date: July 12, 2007
    Inventor: Tsukasa Ooishi
  • Patent number: 7233537
    Abstract: Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: June 19, 2007
    Assignees: Renesas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventors: Hiroaki Tanizaki, Hideto Hidaka, Takaharu Tsuji, Tsukasa Ooishi
  • Publication number: 20070103968
    Abstract: The non-volatile memory device includes a current detection circuit for comparing, in data retrieve operation, storage information written in a non-volatile manner in a memory cell row with retrieval information in order to determine whether or not the storage information matches the retrieval information. The current detection circuit compares a data read current flowing through each bit line corresponding to each memory cell of a memory cell row storing the storage information with a data read current flowing through each bit line corresponding to each retrieval memory cell storing the retrieval information.
    Type: Application
    Filed: December 26, 2006
    Publication date: May 10, 2007
    Inventor: Tsukasa Ooishi