Abstract: A plurality of test target chips on a test target wafer are simultaneously and electrically coupled to a plurality of chips on a test wafer via a wafer contactor. Each chip on the test wafer has a test circuit for conducting an operation test on each chip on the test target wafer. Since the test circuit is in a one-to-one relationship with respect to the test target chip, and is arranged on the test wafer other than the test target wafer, the many chips can be simultaneously tested in parallel during the wafer test without increasing an area of the test target chips.

Abstract: In one data read operation, data read for reading stored data before and after a predetermined data write magnetic field is applied to a selected memory cell, respectively, is executed, and the data read is executed in accordance with comparison of voltage levels corresponding to the data read operations before and after application of the predetermined data write magnetic field. In addition, data read operations before and after the application of a data write magnetic field are executed using read modify write. It is thereby possible to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path, to improve efficiency of the data read operation with accuracy and to execute a high rate data read operation.

Abstract: Bit lines are provided corresponding to columns of MTJ memory cells. Word lines serving as read selection lines and write digit lines serving as write selection lines are provided corresponding to rows of MTJ memory cells. A word line decoder and a digit line decoder are independently provided for the word lines and the write digit lines. The word line decoder selectively activates a word line according to a read address applied to a read port. The digit line decoder selectively activates a write digit line according to a write address applied to a write port.

Abstract: An internal power-source potential supply circuit for supplying an internal power-source potential with high accuracy is disclosed. An external power-source potential (VCE) is connected to the source of a PMOS transistor (Q1) having a drain for applying an internal power-source potential (VCI) to a load (11) and a gate receiving a control signal (S1) from a comparator (1). The comparator (1) outputs the control signal (S1) on the basis of a comparison result between a reference potential (Vref) and a divided internal power-source potential (DCI). The drain of the PMOS transistor (Q1) is connected to a first end of a resistor (R1), and a current source (2) is connected between a second end of the resistor (R1) and ground. A voltage provided at a node (N1) serving as the second end of the resistor (R1) is applied to a positive input of the comparator (1) as the divided internal power-source potential (DCI).

Abstract: In storing multiple data into a storage area of a first nonvolatile memory cell and into a storage area of a second nonvolatile memory cell in a memory cell array, a first control circuit turns on a switch circuit to supply a predetermined write potential to a bit line, and a second control circuit turns on two switch circuits to supply a source potential to each of two bit lines according to the combination of multiple data to be stored in each memory cell.

Abstract: Dummy cells in an erased state and in a write state are used to generate a dummy current corresponding to the average current of currents flowing in the dummy cells using a ½ current generating circuit, and the dummy current is compared with a current corresponding to a memory cell current flowing in a selected normal cell using a current sense amplification circuit to generate internal read data according to a result of the comparison. With such a configuration, a non-volatile semiconductor memory device capable of reading data at high speed can be achieved.

Abstract: A thin film magnetic memory device includes: a TMR element, provided on a main surface of a silicon substrate, operating as a memory element; a buffer layer having a first surface bringing into contact with the TMR element and a second surface, located on the side opposite to the first surface, having an area smaller than that of the first surface; and a bit line, formed of a conductor film and a barrier metal film that bring into contact with the second surface, extending in one direction so as to intersect the TMR element. Thereby, it is possible to provide a thin film magnetic memory device realizing miniaturization of the memory cell and, also, having a high reliability, and a manufacturing method therefor.

Abstract: A non-volatile semiconductor memory device of the present invention is provided with a semiconductor substrate having a main surface, an ONO film (a laminated film of an oxide film, a nitride film and an oxide film) formed on the main surface and having a charge storage part, a pair of buried diffusion bit lines formed in the semiconductor substrate located on both sides of the ONO film, oxide films deposited on the main surface so as to cover the buried diffusion bit lines, and a transfer gate electrode formed on the ONO film.

Abstract: To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrode is formed thereon. Such a device is connected in series to a MOS transistor of the opposite polarity and such arrangements are cross-connected together to form a latch circuit. Data to be programmed and the inverted version thereof are written in the programming device. Programmed information is read depending on the change in weight of the latch when the power supply is turned on.

Abstract: A spare reference cell is provided for a reference cell which is compared to a selected memory cell in read operation. A data read circuit reads storage data of a selected memory cell based on access to the selected memory cell and access to a selected one of the reference cell and the spare reference cell. Selection of the reference cell and the spare reference cell is not fixed according to the result of operation test conducted before a device is used, but can be switched according to various conditions.

Abstract: At a time a voltage of 6V is applied to all word lines and memory cells connected to a bit line are all simultaneously subjected to a weak write operation using a channel hot electron. Furthermore at a subsequent time a voltage of approximately 2V is applied to a word line and any single memory cell connected to the word line is subjected to a verify operation. The series of the weak write and verify operations are repeated until this memory cell's threshold voltage attains 2V corresponding to an erased condition.

Abstract: A plurality of sense amplifiers are connected to a selected bit line. Each sense amplifier is supplied with a residual current corresponding to a current flowing in a memory cell and a reference current serving as a reference for a threshold voltage of the memory cell to sense the currents. Operations of the sense amplifiers are controlled such that different sense margins are provided to different sense amplifiers and a margin failure is detected according to coincidence/non-coincidence in logical level between output signals of the sense amplifiers. The address of a memory cell with the margin failure is registered. With such a construction, a threshold voltage defect of a non-volatile memory cell is compensated for to enable internal reading of memory cell data with correctness.

Abstract: A thin film magnetic memory device includes: TMR elements provided at a predetermined distance away from each other on a main surface of a silicon substrate so as to operate as memory elements; a first digit line for applying a magnetic field to TMR element, extending in one direction so as to intersect TMR element; a second digit line for applying a magnetic field to TMR element, extending parallel to the first digit line so as to intersect TMR element; and a magnetic film provided so as to fill in the space between the first digit line and the second digit line and so as to bring into contact with the first and second digit lines. The present invention provides a thin film magnetic memory device wherein crosstalk can be prevented from generating between adjacent memory cells and wherein wire resistance does not increase.

Abstract: In a DRAM employing a shared sense amplifier method, a bit line select signal falls to the level of ground potential after a potential difference is generated between a pair of bit lines and sense nodes in response to activation of a word line in a self refresh mode for disconnecting the bit line pair in a memory block including the activated word line from a sense amplifier. When the potentials of the sense nodes are amplified by the sense amplifier, the disconnected bit line pair is connected again to the sense amplifier.

Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

Abstract: A thin film magnetic memory device includes an antenna section transmitting and receiving a radio wave to an from an outside of the thin film magnetic memory device. An inductance wiring constituting the antenna section has a metal wiring, and a magnetic film formed to correspond to a lower surface portion of the metal wiring or lower surface and side surface portions of the metal wiring. The magnetic film is formed in an original manufacturing step of the thin film magnetic memory device without providing a dedicated manufacturing step.

Abstract: A semiconductor integrated circuit device includes a plurality of internal circuits, internal potential generating circuits for converting a level of an external power supply potential to supply an internal potential at a level corresponding to a level set signal, a control portion for successively applying the plurality of level set signals to each of the internal potential generating circuits, and a measuring circuit for comparing each internal potential with a reference potential, and holding information representing results of the comparison. During a test period, a comparing circuit in the internal potential generating circuit compares a level corresponding to the level set signal with a comparison reference potential.

Abstract: A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

Abstract: Bit lines formed from a first metal wiring layer and bit lines formed from a second metal wiring layer are provided as bit lines that intersect with word lines. The bit lines are formed from metal wiring layers and are divided into two layers so that the pitch of the bit lines can be widened. Thereby, a non-volatile semiconductor memory device having an increased access speed while maintaining production yield can be implemented.

Abstract: A memory cell array has a plurality of memory cells and dummy memory cells. A column select portion switches access control to a memory cell in accordance with a mode control signal. The column select portion selects one memory cell column to connect a first or second bit line connected with one selected memory cell and first and second reference data lines connected with the dummy memory cells to a data read circuit in a first mode. The column select portion connects the first and second bit lines respectively connected to paired two selected memory cells storing data complimentary to each other to the data read circuit in a second mode.