Patents by Inventor Tsukasa Shiraishi

Tsukasa Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080283284
    Abstract: A wiring board connection method connects wiring boards each having a strip-shaped connection terminal for connecting with another substrate, the method including the steps of: aligning the wiring boards so that the connection terminals face each other with a fluid interposed therebetween; and bonding the connection terminals with each other by heating and then-cooling the fluid, wherein: the fluid is a material that generates air bubbles upon being heated; a plurality of the connection terminals are provided on each of the wiring boards; and a groove is formed in each of at least one of the connection terminals in at least one of the wiring boards, the groove extending across the relevant connection terminal.
    Type: Application
    Filed: May 15, 2008
    Publication date: November 20, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayoshi KOYAMA, Tsukasa SHIRAISHI
  • Publication number: 20080265437
    Abstract: A highly reliable, high-productivity package equipped with a semiconductor chip, and a method for producing the same. In a package (100) comprising a semiconductor chip (10) and a mounting substrate (30), a plurality of electrode terminals (12) are formed on the surface (10a) of the semiconductor chip (10) opposing the mounting substrate side, connection terminals (32) respectively corresponding to the plurality of electrode terminals (12), are formed on the mounting substrate (30), the connection terminals (32) on the mounting substrate (30) and the electrode terminals (12) are electrically connected collectively by solder bumps (17) formed in self-assembly, an electrode pattern (20) not connected with the electrode terminals (12) and the connection terminals (32) is formed on the chip surface (10a) or the surface (35) of the mounting substrate (30) corresponding to the chip surface (10a), and solder (19) is accumulated on the electrode pattern (20).
    Type: Application
    Filed: March 8, 2006
    Publication date: October 30, 2008
    Inventors: Tsukasa Shiraishi, Yukihiro Ishimaru, Seiji Karashima, Seiichi Natkatani, Hiroki Yabe
  • Publication number: 20080186045
    Abstract: An inspection mark structure has an inspection via hole, which is provided in substrate sheets to be heat-pressed constituting at least two layers of laminates; a round pattern electrode, which is formed on one main face side of the substrate sheet provided with the inspection via hole, and provided around the end face of the inspection via hole at such a predetermined distance as not to come into contact with the end face; and a conduction electrode, which is formed on the other main face side of the substrate sheet provided with the inspection via hole, and provided so as to be electrically connected with the end face of the inspection via hole.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 7, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoji UEDA, Tsukasa SHIRAISHI, Yositake HAYASHI, Rikiya OKIMOTO
  • Publication number: 20080011402
    Abstract: A liquid resin in which conductive particles are dispersed is supplied to between a circuit substrate and a semiconductor chip disposed so as to face each other and an ultrasonic wave having an amplitude in a perpendicular direction to a surface of the circuit substrate to generate a standing wave in a resin. Then, the conductive particles dispersed in the resin are captured at nodes of the standing wave to form connection bodies of aggregation of the conductive particles between connection terminals of the semiconductor chip and terminals of the circuit substrate. Thus, the semiconductor chip is mounted on the circuit substrate via the connection bodies. The terminals are arrayed so as to be spaced apart from one another by half a wavelength of the standing wave and each of the nodes of the standing wave are generated at a position between the terminals in the resin.
    Type: Application
    Filed: April 11, 2007
    Publication date: January 17, 2008
    Inventors: Tsukasa Shiraishi, Seiichi Nakatani
  • Publication number: 20070262447
    Abstract: A circuit board 1 having a base material 10 and an electrode 11 formed on at least one main surface of the base material 10 includes an easy peeling portion 12 formed in at least one of an inner portion and a side portion of the electrode 11, with the adhesive strength between the electrode 11 and the easy peeling portion 12 being less than the adhesive strength between the electrode 11 and the base material 10. A circuit board that has high connection reliability and enables narrow pitch mounting thereby can be provided.
    Type: Application
    Filed: May 14, 2007
    Publication date: November 15, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Koichi HIRANO, Tsukasa SHIRAISHI, Seiichi NAKATANI, Tatsuo OGAWA
  • Publication number: 20060087020
    Abstract: In a semiconductor device, circuit boards are connected electrically to each other by via-conductors that penetrate sheet members, semiconductor elements arranged between substrates are contained in element-containing portions formed on the sheet members, and a low-elastic material whose elastic modulus is lower than the elastic modulus of the thermosetting resin composition of the sheet members is filled in the space between the semiconductor elements contained in the element-containing portions and the substrates opposing surfaces opposite to the mounting surfaces of the semiconductor elements. Thereby, a semiconductor device resistant to warping and deformation and having a high mounting reliability is provided.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 27, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Koichi Hirano, Seiichi Nakatani, Tsukasa Shiraishi, Yoshitake Hayashi
  • Publication number: 20050163982
    Abstract: The invention is intended for providing a semiconductor package structure which prevents degradation in characteristics of a semiconductor device, and breakage of interconnections, when the semiconductor device is packaged on a circuit substrate. In the package structure having the semiconductor device mounted on the circuit substrate, bump electrodes of the semiconductor device are placed on input/output terminal electrodes of the circuit substrate and are electrically and mechanically connected thereto by bonding with a conductive adhesive, and the semiconductor device is bonded and fixed to the circuit substrate by a resin film formed previously on a surface of a main body of the circuit substrate. The structure does no damage to a semiconductor functional part and to interconnections, and allows mounting with a lower load as compared to structures using conventional anisotropic conductive films and the like.
    Type: Application
    Filed: January 24, 2005
    Publication date: July 28, 2005
    Inventors: Masahiro Ono, Tsukasa Shiraishi
  • Patent number: 6909180
    Abstract: The invention is intended for providing a semiconductor package structure which prevents degradation in characteristics of a semiconductor device, and breakage of interconnections, when the semiconductor device is packaged on a circuit substrate. In the package structure having the semiconductor device mounted on the circuit substrate, bump electrodes of the semiconductor device are placed on input/output terminal electrodes of the circuit substrate and are electrically and mechanically connected thereto by bonding with a conductive adhesive, and the semiconductor device is bonded and fixed to the circuit substrate by a resin film formed previously on a surface of a main body of the circuit substrate. The structure does no damage to a semiconductor functional part and to interconnections, and allows mounting with a lower load as compared to structures using conventional anisotropic conductive films and the like.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: June 21, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Ono, Tsukasa Shiraishi
  • Patent number: 6818461
    Abstract: A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting portion of the substrate by means of an electrically conductive adhesive. A region of the semiconductor device which is not involved in electrical connection is bonded to a region of the substrate which is not involved in electrical connection by means of an adhesive. A test of electrical properties is performed on the semiconductor device and the substrate which are connected to each other. If it is determined that the electrical properties are poor in the test, the semiconductor device is separated from the substrate after heating a bonding place of the adhesive up to a temperature higher than a glass transition point or a melting point of the adhesive. If it is determined that the electrical properties are good in the test, the semiconductor device and the substrate are sealed by means of a sealing resin.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: November 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyoshi Amami, Tsukasa Shiraishi, Yoshihiro Bessho
  • Publication number: 20040212075
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Application
    Filed: May 20, 2004
    Publication date: October 28, 2004
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 6756663
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 6694613
    Abstract: A method for producing a printed-circuit board includes forming via holes that penetrate through a prepreg to whose surface a parting film is applied; filling the via holes with a conducting paste; compressing the prepreg under heat to cure the prepreg and the paste; and then peeling off the parting film. Thus, projection electrodes with a height corresponding to the thickness of the film are formed in a manner such that the projection electrodes are integrated with the via hole conductors.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: February 24, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshifumi Nakamura, Minehiro Itagaki, Hiroaki Takezawa, Yoshihiro Bessho, Tsukasa Shiraishi
  • Publication number: 20030094685
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Application
    Filed: January 8, 2003
    Publication date: May 22, 2003
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Publication number: 20030049425
    Abstract: The invention is intended for providing a semiconductor package structure which prevents degradation in characteristics of a semiconductor device and breakage of the interconnections when the semiconductor device is packaged on a circuit substrate. In the package structure having the semiconductor device mounted on the circuit substrate, bump electrodes of the semiconductor device are placed on input/output terminal electrodes of the circuit substrate and are electrically and mechanically connected thereto by bonding with conductive adhesive, and the semiconductor device is bonded and fixed to the circuit substrate by a resin film formed previously on a surface of the substrate. The structure does no damage to a semiconductor functional part and to interconnections, and allows mounting with a lower load in comparison with structures using conventional anisotropic conductive films and the like, so that heat-press bonding mounting with a high productivity and a low cost can be applied.
    Type: Application
    Filed: January 11, 2002
    Publication date: March 13, 2003
    Inventors: Masahiro Ono, Tsukasa Shiraishi
  • Patent number: 6525414
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: February 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 6452280
    Abstract: A semiconductor apparatus in which the height of the projected electrode (4) formed on the semiconductor element (1) is deformed plastically so as to unify the distance of the protruding surface of the projected electrode (4) and the surface of the electrode terminal (7) at the side of the circuit substrate (5), and the semiconductor element and the circuit substrate are connected electrically with reliability. A method for producing the semiconductor apparatus also is disclosed. After the semiconductor element (1) is positioned on the predetermined part of the circuit substrate (5), the projected electrode (4) is deformed plastically by pushing the semiconductor element (1) from the back and the height of the projected electrode (4) is processed appropriately.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: September 17, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsukasa Shiraishi, Yoshihiro Bessho
  • Patent number: 6429382
    Abstract: For the reliability in insulation and against sulfurization, the mounting structure of the invention includes an electric structure, and an electrically conductive adhesive layer including an electrically conductive filler disposed on the electric structure, and at least a portion of surface of the electrically conductive filler is exposed to an external environment, and an elution preventive film is disposed on at least a portion of the exposed surface. Further, an electrically conductive adhesive of this invention includes the electrically conductive filler, and an elution preventive film is disposed on the entire surface of the electrically conductive filler.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: August 6, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyoshi Amami, Hiroaki Takezawa, Tsukasa Shiraishi, Yoshihiro Bessho
  • Publication number: 20020072151
    Abstract: A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting portion of the substrate by means of an electrically conductive adhesive. A region of the semiconductor device which is not involved in electrical connection is bonded to a region of the substrate which is not involved in electrical connection by means of an adhesive. A test of electrical properties is performed on the semiconductor device and the substrate which are connected to each other. If it is determined that the electrical properties are poor in the test, the semiconductor device is separated from the substrate after heating a bonding place of the adhesive up to a temperature higher than a glass transition point or a melting point of the adhesive. If it is determined that the electrical properties are good in the test, the semiconductor device and the substrate are sealed by means of a sealing resin.
    Type: Application
    Filed: February 5, 2002
    Publication date: June 13, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kazuyoshi Amami, Tsukasa Shiraishi, Yoshihiro Bessho
  • Patent number: 6369450
    Abstract: A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting portion of the substrate by means of an electrically conductive adhesive. A region of the semiconductor device which is not involved in electrical connection is bonded to a region of the substrate which is not involved in electrical connection by means of an adhesive. A test of electrical properties is performed on the semiconductor device and the substrate which are connected to each other. If it is determined that the electrical properties are poor in the test, the semiconductor device is separated from the substrate after heating a bonding place of the adhesive up to a temperature higher than a glass transition point or a melting point of the adhesive. If it is determined that the electrical properties are good in the test, the semiconductor device and the substrate are sealed by means of a sealing resin.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: April 9, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyoshi Amani, Tsukasa Shiraishi, Yoshihiro Bessho
  • Publication number: 20010033032
    Abstract: A manufacturing method for a semiconductor device using a wire bonding method using a metal wire. In the wire bonding method, an impact load applied when a metal ball formed at the tip of the metal wire by electric discharge is brought into contact with a terminal electrode of a semiconductor device is smaller than a static load applied after the metal ball is brought into contact with the terminal electrode. The method makes it possible to prevent an element or wiring from being damaged while securing the pressure necessary for bonding the metal ball to the terminal electrode even when the terminal electrode is placed on the element or the wiring.
    Type: Application
    Filed: April 25, 2001
    Publication date: October 25, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Ono, Tsukasa Shiraishi, Yoshihiro Bessho, Kazuo Eda