Patents by Inventor Tsukasa TOKUTOMI

Tsukasa TOKUTOMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11367489
    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: June 21, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
  • Publication number: 20220130468
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Application
    Filed: January 4, 2022
    Publication date: April 28, 2022
    Applicant: Kioxia Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA
  • Patent number: 11315643
    Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: April 26, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa
  • Publication number: 20220115070
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: KIOXIA CORPORATION
    Inventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
  • Publication number: 20220077175
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Takuya FUTATSUYAMA
  • Publication number: 20220076773
    Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m?1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.
    Type: Application
    Filed: February 26, 2021
    Publication date: March 10, 2022
    Inventors: Tsukasa TOKUTOMI, Kiwamu WATANABE, Riki SUZUKI, Toshikatsu HIDA, Takahiro ONAGI
  • Publication number: 20220044738
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 10, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Kengo KUROSE, Marie TAKADA, Ryo YAMAKI, Kiyotaka IWASAKI, Yoshihisa KOJIMA
  • Patent number: 11238936
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: February 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
  • Patent number: 11222703
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: January 11, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Shohei Asami, Masamichi Fujiwara
  • Publication number: 20220005537
    Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.
    Type: Application
    Filed: September 15, 2021
    Publication date: January 6, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Kiwamu WATANABE, Kengo KUROSE
  • Patent number: 11211396
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: December 28, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Takuya Futatsuyama
  • Patent number: 11211138
    Abstract: A memory system includes a memory chip and a memory controller. The memory chip has a first plane and a second plane. A threshold voltage corresponding to multiple bit data is set for each of the memory cells. The memory controller causes the memory chip to execute a first read process on the first plane and the second plane in parallel by using a plurality of first read voltages different from each other for the first plane and the second plane. The first read process being a process of reading a data group of one bit among the multiple bits by using the first read voltages. The memory controller subsequently adjusts the voltage levels of the first read voltages on the basis of the data group read from the memory cells of the first plane and the data group read from the memory cells of the second plane.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: December 28, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Tsukasa Tokutomi, Kiwamu Watanabe, Yuko Noda
  • Patent number: 11195585
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: December 7, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kengo Kurose, Marie Takada, Ryo Yamaki, Kiyotaka Iwasaki, Yoshihisa Kojima
  • Publication number: 20210334046
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.
    Type: Application
    Filed: July 8, 2021
    Publication date: October 28, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Marie TAKADA, Masanobu SHIRAKAWA, Tsukasa TOKUTOMI
  • Patent number: 11152075
    Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: October 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kiwamu Watanabe, Kengo Kurose
  • Patent number: 11086573
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: August 10, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Marie Takada, Masanobu Shirakawa, Tsukasa Tokutomi
  • Publication number: 20210165713
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
  • Patent number: 11017863
    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 25, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
  • Patent number: 11004523
    Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 11, 2021
    Assignee: Toshiba Memory Coiporation
    Inventors: Riki Suzuki, Masanobu Shirakawa, Yoshihisa Kojima, Marie Takada, Tsukasa Tokutomi
  • Publication number: 20210110875
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA