Patents by Inventor Tsukasa TOKUTOMI
Tsukasa TOKUTOMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094957Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicant: KIOXIA CORPORATIONInventors: Marie TAKADA, Masanobu SHIRAKAWA, Tsukasa TOKUTOMI
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Patent number: 11915759Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.Type: GrantFiled: December 20, 2021Date of Patent: February 27, 2024Assignee: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
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Patent number: 11892907Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: GrantFiled: November 10, 2022Date of Patent: February 6, 2024Assignee: Kioxia CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
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Publication number: 20240021250Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.Type: ApplicationFiled: July 31, 2023Publication date: January 18, 2024Applicant: KIOXIA CORPORATIONInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA
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Patent number: 11875063Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.Type: GrantFiled: December 16, 2022Date of Patent: January 16, 2024Assignee: KIOXIA CORPORATIONInventors: Marie Takada, Masanobu Shirakawa, Tsukasa Tokutomi
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Publication number: 20230402106Abstract: A memory controller receives first, second, and third data by first, second, and third reads, specifying a first address, and respectively specifying first, second, and third read voltages higher in this order. The controller instructs a memory to execute a fourth read specifying a fourth read voltage lower than the first read voltage and the first address when a first difference between a first-value-bit count of the first data and an expected value is smaller than a second difference between a first-value-bit count of the third data and the expected value. The memory controller instructs the memory to execute a fifth read specifying a fifth read voltage higher than the third read voltage and the first address when the first difference is larger than the second difference.Type: ApplicationFiled: March 3, 2023Publication date: December 14, 2023Applicant: Kioxia CorporationInventors: Masahiro SAITO, Kiwamu WATANABE, Yuko NODA, Tsukasa TOKUTOMI, Yoshiki TAKAI
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Publication number: 20230360714Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Applicant: KIOXIA CORPORATIONInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Kiwamu WATANABE, Kengo KUROSE
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Semiconductor storage device and memory system including semiconductor storage device and controller
Patent number: 11790986Abstract: A memory system is provided, including a semiconductor storage device including memory cells that can store data of n bits, and a word line connected to the cells; and a memory controller to control the device and being configured to send a first read request, in response to which the device can perform a first read operation of reading first data out of the cells with a first voltage applied to the word line, to send a second read request, in response to which the device can perform a second read operation of reading second data out of the cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, perform a first logical operation of logically processing the first and the second data, and send third data generated by the first logical operation to the controller.Type: GrantFiled: July 27, 2022Date of Patent: October 17, 2023Assignee: Kioxia CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada -
Patent number: 11763893Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.Type: GrantFiled: January 4, 2022Date of Patent: September 19, 2023Assignee: Kioxia CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Shohei Asami, Masamichi Fujiwara
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Patent number: 11756642Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.Type: GrantFiled: September 15, 2021Date of Patent: September 12, 2023Assignee: Kioxia CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kiwamu Watanabe, Kengo Kurose
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Publication number: 20230274784Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Applicant: KIOXIA CORPORATIONInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA
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Publication number: 20230223090Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.Type: ApplicationFiled: February 27, 2023Publication date: July 13, 2023Applicant: KIOXIA CORPORATIONInventors: Masanobu SHIRAKAWA, Tsukasa TOKUTOMI, Marie TAKADA
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Patent number: 11699499Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m?1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.Type: GrantFiled: February 26, 2021Date of Patent: July 11, 2023Assignee: Kioxia CorporationInventors: Tsukasa Tokutomi, Kiwamu Watanabe, Riki Suzuki, Toshikatsu Hida, Takahiro Onagi
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Patent number: 11682464Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.Type: GrantFiled: March 16, 2022Date of Patent: June 20, 2023Assignee: KIOXIA CORPORATIONInventors: Tsukasa Tokutomi, Masanobu Shirakawa
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Publication number: 20230117717Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.Type: ApplicationFiled: December 16, 2022Publication date: April 20, 2023Applicant: KIOXIA CORPORATIONInventors: Marie TAKADA, Masanobu SHIRAKAWA, Tsukasa TOKUTOMI
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Patent number: 11626167Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.Type: GrantFiled: December 22, 2020Date of Patent: April 11, 2023Assignee: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Tsukasa Tokutomi, Marie Takada
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Publication number: 20230065159Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: ApplicationFiled: November 10, 2022Publication date: March 2, 2023Applicant: Kioxia CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
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Patent number: 11561736Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.Type: GrantFiled: July 8, 2021Date of Patent: January 24, 2023Assignee: KIOXIA CORPORATIONInventors: Marie Takada, Masanobu Shirakawa, Tsukasa Tokutomi
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Patent number: 11537465Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: GrantFiled: February 12, 2021Date of Patent: December 27, 2022Assignee: KIOXIA CORPORATIONInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
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SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM INCLUDING SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER
Publication number: 20220375516Abstract: A memory system is provided, including a semiconductor storage device including memory cells that can store data of n bits, and a word line connected to the cells; and a memory controller to control the device and being configured to send a first read request, in response to which the device can perform a first read operation of reading first data out of the cells with a first voltage applied to the word line, to send a second read request, in response to which the device can perform a second read operation of reading second data out of the cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, perform a first logical operation of logically processing the first and the second data, and send third data generated by the first logical operation to the controller.Type: ApplicationFiled: July 27, 2022Publication date: November 24, 2022Applicant: Kioxia CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA