Abstract: A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.

Abstract: A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.

Abstract: An inductor structure comprising a substrate; a plurality of insulation layers on the substrate; a first spiral electric conductive coil positioned in the insulation layers to form an inductor having a first direction of magnetic field; a second spiral electric conductive coil positioned in the insulation layers to form an inductor having a second direction of magnetic field, in which, the two or more inductors are independently positioned in a same 3-D space and have a good integration.

Abstract: A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and not electrically connected to the closed conductive ring. The major conductive bars and the minor conductive bars of an odd layer conductive pattern are respectively corresponding to the minor conductive bars and the major conductive bars of an even layer conductive pattern.

Abstract: A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and not electrically connected to the closed conductive ring. The major conductive bars and the minor conductive bars of an odd layer conductive pattern are respectively corresponding to the minor conductive bars and the major conductive bars of an even layer conductive pattern.

Abstract: A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.

Abstract: A semiconductor structure comprising a first conductive type substrate, a first conductive type well, an integrated circuit region, an isolation structure and a second conductive type doped region is described. The first conductive type well is disposed in the first conductive type substrate. The integrated circuit region is disposed in the first conductive type well. The isolation structure is disposed in the first conductive type substrate around the integrated circuit region. The second conductive type doped region is disposed in the first conductive type substrate around the isolation structure.

Abstract: A capacitor structure is described, including a first capacitor and a second capacitor. The first capacitor includes a first electrode, a second electrode and a first insulating layer, wherein the second electrode is disposed under the first electrode and the first insulating layer between the first electrode and the second electrode. The second capacitor is disposed under the first capacitor and coupled thereto in parallel. The second capacitor includes multiple patterned metal layers and via plugs that constitute a third electrode and a fourth electrode, and a second insulating layer. The patterned metal layers are stacked in the second insulating layer and connected by the via plugs, wherein each patterned metal layer includes a portion of the third electrode and a portion of the fourth electrode that are separated by the second insulating layer.

Abstract: An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.

Abstract: A substrate isolation design includes a P substrate, a P well positioned on the P substrate, at least a device positioned in the P well, and at least a P substrate guard ring surrounding the device. A P+ guard ring, an N well guard ring, or a deep N well guard ring can be selectively interposed between the P substrate guard ring and the device to facilitate blocking substrate coupling effect.

Abstract: A substrate isolation design includes a P substrate, a P well positioned on the P substrate, at least a device positioned in the P well, and at least a P substrate guard ring surrounding the device. A P+ guard ring, an N well guard ring, or a deep N well guard ring can be selectively interposed between the P substrate guard ring and the device to facilitate blocking substrate coupling effect.

Abstract: An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.

Abstract: A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.

Abstract: A fabrication method of an electrostatic discharge protection circuit is described, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.

Abstract: A structure of an electrostatic discharge protection circuit, using a deep trench structure to replace the guard ring at a periphery of the electrostatic discharge protection circuit. Consequently, the device area is smaller compared to the device with the guard ring. Moreover, the device area is further reduced because the distance between the transistors of the electrostatic discharge protection circuit is shortened. At the same time, the functions of latch-up immunity and substrate noise immunity are more effective.

Abstract: A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.

Abstract: A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.