Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Abstract: The present disclosure provides a semiconductor memory device and a method of fabricating the same, with the semiconductor memory device including a substrate, a plurality of capacitor structures, a stress insulating layer, and at least one interface layer. The capacitor structures are separately disposed on the substrate, and each of the capacitor structures includes a plurality of capacitors. The stress insulating layer is disposed on the substrate to cover the capacitor structures. The interface layer is disposed within the stress insulating layer, between any two adjacent ones of the capacitor structures, wherein a tip portion of the at least one interface layer is higher than a top surface of each of the capacitor structures. In this way, the stress mode of the substrate may be adjusted through disposing the interface layer, so as to achieve the effect of eliminating redundant stress, and to improve the structural reliability of the device.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.

Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.

Abstract: A semiconductor structure and method for forming such a structure are disclosed by the present invention. In the method, before a first trench in a pre-processed substrate is filled with any filling material, an auxiliary layer is formed over an inner surface of the first trench. Afterward, a first filling dielectric is formed and an etch back process is performed so that a top surface of the first filling dielectric is higher than that of the pre-processed substrate, and a second filling dielectric is then formed and subject to a second planarization process.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.