Patents by Inventor Tsun-Min Cheng

Tsun-Min Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10475900
    Abstract: A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C.-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kai-Jiun Chang, Tsun-Min Cheng, Chih-Chieh Tsai, Jui-Min Lee, Yi-Wei Chen, Chia-Lung Chang, Wei-Hsin Liu
  • Patent number: 10475799
    Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Yi-Wei Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Tsun-Min Cheng, Chi-Mao Hsu
  • Patent number: 10465287
    Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 5, 2019
    Assignees: UNITED MICROELECTRONCIS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Pin-Hong Chen, Tsun-Min Cheng, Yi-Wei Chen
  • Publication number: 20190318933
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Application
    Filed: May 22, 2018
    Publication date: October 17, 2019
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20190319107
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Application
    Filed: May 22, 2018
    Publication date: October 17, 2019
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Publication number: 20190249297
    Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.
    Type: Application
    Filed: March 12, 2018
    Publication date: August 15, 2019
    Inventors: Chih-Chien Liu, Pin-Hong Chen, Tsun-Min Cheng, Yi-Wei Chen
  • Publication number: 20190252390
    Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 15, 2019
    Inventors: Yi-Wei Chen, Pin-Hong Chen, Tsun-Min Cheng, Chun-Chieh Chiu
  • Patent number: 10374051
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a metal silicon nitride layer on the silicon layer; forming a stress layer on the metal silicon nitride layer; performing a thermal treatment process; removing the stress layer; forming a conductive layer on the metal silicon nitride layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ji-Min Lin, Yi-Wei Chen, Tsun-Min Cheng, Pin-Hong Chen, Chih-Chien Liu, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chieh Tsai, Yi-An Huang, Kai-Jiun Chang
  • Publication number: 20190237468
    Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 1, 2019
    Inventors: Pin-Hong Chen, Yi-Wei Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Tsun-Min Cheng, Chi-Mao Hsu
  • Patent number: 10323332
    Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: June 18, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ling Lin, Yen-Liang Lu, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Chi-Ray Tsai
  • Patent number: 10312242
    Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 4, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chieh Chen, Pin-Hong Chen, Chih-Chieh Tsai, Chia-Chen Wu, Yi-An Huang, Kai-Jiun Chang, Tsun-Min Cheng, Yi-Wei Chen
  • Patent number: 10290638
    Abstract: A method of forming dynamic random access memory (DRAM) device, comprises the following steps. First of all, a plurality of active areas is formed in a substrate along a first direction. Next, a plurality of buried gates disposed in the substrate is formed along a second trench extending along a second direction across the first direction. Then, a plurality of bit lines is formed over the buried gates and extended along a third direction across the first direction and the second direction, wherein each of the bit lines comprises a polysilicon layer, a barrier layer and a metal layer and the barrier layer is formed through a radio frequency physical vapor deposition (RF-PVD) process.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: May 14, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Tsun-Min Cheng, Shih-Fang Tzou, Chih-Chieh Tsai, Kai-Jiun Chang
  • Patent number: 10276389
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the silicon layer; performing an oxygen treatment process to form an oxide layer on the first metal silicon nitride layer; forming a second metal silicon nitride layer on the oxide layer; forming a conductive layer on the second metal silicon nitride layer; and patterning the conductive layer, the second metal silicon nitride layer, the oxide layer, the first metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Yi-Wei Chen, Pin-Hong Chen, Chih-Chien Liu, Tzu-Chieh Chen, Chun-Chieh Chiu, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang
  • Publication number: 20190067296
    Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
    Type: Application
    Filed: September 22, 2017
    Publication date: February 28, 2019
    Inventors: Pin-Hong Chen, Yi-Wei Chen, Tzu-Chieh Chen, Chih-Chieh Tsai, Chia-Chen Wu, Kai-Jiun Chang, Yi-An Huang, Tsun-Min Cheng
  • Patent number: 10211211
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a barrier layer in the trench; performing a soaking process to reduce chlorine concentration in the barrier layer; and forming a conductive layer to fill the trench.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: February 19, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kai-Jiun Chang, Yi-Wei Chen, Tsun-Min Cheng, Chia-Chen Wu, Pin-Hong Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Yi-An Huang
  • Patent number: 10199228
    Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Nien-Ting Ho, Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Wei-Yu Chen, Min-Chuan Tsai, Tsun-Min Cheng, Chi-Mao Hsu
  • Publication number: 20190027479
    Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.
    Type: Application
    Filed: May 29, 2018
    Publication date: January 24, 2019
    Inventors: Chia-Chen Wu, Yi-Wei Chen, Chi-Mao Hsu, Kai-Jiun Chang, Chih-Chieh Tsai, Pin-Hong Chen, Tsun-Min Cheng, Yi-An Huang
  • Publication number: 20190013320
    Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.
    Type: Application
    Filed: May 22, 2018
    Publication date: January 10, 2019
    Inventors: Tzu-Chieh Chen, Pin-Hong Chen, Chih-Chieh Tsai, Chia-Chen Wu, Yi-An Huang, Kai-Jiun Chang, Tsun-Min Cheng, Yi-Wei Chen
  • Publication number: 20180350673
    Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.
    Type: Application
    Filed: March 21, 2018
    Publication date: December 6, 2018
    Inventors: Pin-Hong Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Tsun-Min Cheng, Yi-Wei Chen, Wei-Hsin Liu
  • Publication number: 20180337187
    Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
    Type: Application
    Filed: July 5, 2018
    Publication date: November 22, 2018
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou