Patents by Inventor Tsunekazu SAIMEI

Tsunekazu SAIMEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11532736
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: December 20, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
  • Patent number: 11049835
    Abstract: A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad provided on the PCB base, a semiconductor die provided on the conductive die pad, and a conductive die bonding agent that electrically connects the conductive die pad and the semiconductor die. The semiconductor module further includes a wire bonding pad provided on the PCB base, a wire that electrically connects the wire bonding pad and the semiconductor die, and a sealing resin that seals the conductive die pad, the semiconductor die, the conductive die bonding agent, the wire bonding pad, and the wire. In a planar view, the area of the conductive die pad is 5.0 mm2 or less.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 29, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tsunekazu Saimei, Takeshi Suzuki, Masashi Yamaura
  • Publication number: 20210184022
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Application
    Filed: March 1, 2021
    Publication date: June 17, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Daisuke TOKUDA, Tsunekazu SAIMEI, Hiroaki TOKUYA
  • Patent number: 10978579
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 13, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
  • Patent number: 10636897
    Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm?3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm?3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm?2), and an n-type GaAs layer Si concentration: about 5×1015 cm?3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm?2.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 28, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Atsushi Kurokawa, Tsunekazu Saimei
  • Publication number: 20190333890
    Abstract: A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad provided on the PCB base, a semiconductor die provided on the conductive die pad, and a conductive die bonding agent that electrically connects the conductive die pad and the semiconductor die. The semiconductor module further includes a wire bonding pad provided on the PCB base, a wire that electrically connects the wire bonding pad and the semiconductor die, and a sealing resin that seals the conductive die pad, the semiconductor die, the conductive die bonding agent, the wire bonding pad, and the wire. In a planar view, the area of the conductive die pad is 5.0 mm2 or less.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 31, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Tsunekazu Saimei, Takeshi Suzuki, Masashi Yamaura
  • Publication number: 20190333887
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Daisuke TOKUDA, Tsunekazu SAIMEI, Hiroaki TOKUYA
  • Patent number: 10404226
    Abstract: A power amplifier module includes a substrate, a power amplifier having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces a principal surface of the substrate, a surface acoustic wave duplexer having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces the principal surface of the substrate, a heat dissipation unit defined on another principal surface of the substrate, a heat dissipation path that connects a connecting portion between the power amplifier and the principal surface to the heat dissipation unit, an insulating resin that covers the power amplifier and the surface acoustic wave duplexer, a conductive shield that covers the insulating resin, and a first conductive unit defined on the second surface of the surface acoustic wave duplexer and electrically connected to the conductive shield.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 3, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takashi Kitahara, Hiroaki Nakayama, Tsunekazu Saimei, Hiroki Noto, Koichiro Kawasaki
  • Patent number: 10403593
    Abstract: A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad provided on the PCB base, a semiconductor die provided on the conductive die pad, and a conductive die bonding agent that electrically connects the conductive die pad and the semiconductor die. The semiconductor module further includes a wire bonding pad provided on the PCB base, a wire that electrically connects the wire bonding pad and the semiconductor die, and a sealing resin that seals the conductive die pad, the semiconductor die, the conductive die bonding agent, the wire bonding pad, and the wire. In a planar view, the area of the conductive die pad is 5.0 mm2 or less.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: September 3, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tsunekazu Saimei, Takeshi Suzuki, Masashi Yamaura
  • Patent number: 10388623
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: August 20, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
  • Publication number: 20190067460
    Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm?3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm?3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm?2), and an n-type GaAs layer Si concentration: about 5×1015 cm?3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm?2.
    Type: Application
    Filed: October 25, 2018
    Publication date: February 28, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Atsushi KUROKAWA, Tsunekazu SAIMEI
  • Patent number: 10147809
    Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm?3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm?3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm?2), and an n-type GaAs layer Si concentration: about 5×1015 cm?3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm?2.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: December 4, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Atsushi Kurokawa, Tsunekazu Saimei
  • Publication number: 20180233475
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 16, 2018
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunari UMEMOTO, Daisuke TOKUDA, Tsunekazu SAIMEI, Hiroaki TOKUYA
  • Publication number: 20180166412
    Abstract: A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad provided on the PCB base, a semiconductor die provided on the conductive die pad, and a conductive die bonding agent that electrically connects the conductive die pad and the semiconductor die. The semiconductor module further includes a wire bonding pad provided on the PCB base, a wire that electrically connects the wire bonding pad and the semiconductor die, and a sealing resin that seals the conductive die pad, the semiconductor die, the conductive die bonding agent, the wire bonding pad, and the wire. In a planar view, the area of the conductive die pad is 5.0 mm2 or less.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 14, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Tsunekazu Saimei, Takeshi Suzuki, Masashi Yamaura
  • Patent number: 9991217
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: June 5, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
  • Publication number: 20170317002
    Abstract: A power amplifier module includes a substrate, a power amplifier having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces a principal surface of the substrate, a surface acoustic wave duplexer having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces the principal surface of the substrate, a heat dissipation unit defined on another principal surface of the substrate, a heat dissipation path that connects a connecting portion between the power amplifier and the principal surface to the heat dissipation unit, an insulating resin that covers the power amplifier and the surface acoustic wave duplexer, a conductive shield that covers the insulating resin, and a first conductive unit defined on the second surface of the surface acoustic wave duplexer and electrically connected to the conductive shield.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 2, 2017
    Inventors: Takashi Kitahara, Hiroaki Nakayama, Tsunekazu Saimei, Hiroki Noto, Koichiro Kawasaki
  • Publication number: 20170077054
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Application
    Filed: November 25, 2016
    Publication date: March 16, 2017
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunari UMEMOTO, Daisuke TOKUDA, Tsunekazu SAIMEI, Hiroaki TOKUYA
  • Patent number: 9508669
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: November 29, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
  • Publication number: 20160315060
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Application
    Filed: July 6, 2016
    Publication date: October 27, 2016
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunari UMEMOTO, Daisuke TOKUDA, Tsunekazu SAIMEI, Hiroaki TOKUYA
  • Publication number: 20160133732
    Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm?3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm?3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm?2), and an n-type GaAs layer Si concentration: about 5×1015 cm?3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm?2.
    Type: Application
    Filed: January 5, 2016
    Publication date: May 12, 2016
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunari UMEMOTO, Atsushi KUROKAWA, Tsunekazu SAIMEI