Abstract: A testing probe system includes probes configured to contact shared probe pads of multi-channel die of a wafer; and a controller configured to generate testing patterns and receive signals from the multi-channel die of the wafer. The controller is configured to contact a probe of the probes with a shared probe pad of the multi-channel die, select a first channel of the multi-channel die to test, select at least one test mode for testing the first channel, stimulate at least the first channel during a single contact period, acquiring a first output of the first channel during the single contact period, select a second channel of the multi-channel die to test, select at least one test mode for testing the second channel, stimulate at least the second channel during the single contact period, and acquire a second output of the first channel during the single contact period.

Abstract: A testing probe system includes probes configured to contact shared probe pads of multi-channel die of a wafer; and a controller configured to generate testing patterns and receive signals from the multi-channel die of the wafer. The controller is configured to contact a probe of the probes with a shared probe pad of the multi-channel die, select a first channel of the multi-channel die to test, select at least one test mode for testing the first channel, stimulate at least the first channel during a single contact period, acquiring a first output of the first channel during the single contact period, select a second channel of the multi-channel die to test, select at least one test mode for testing the second channel, stimulate at least the second channel during the single contact period, and acquire a second output of the first channel during the single contact period.

Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Abstract: A semiconductor device includes: a clock generator generating a first internal clock signal based on an external clock signal; a clock divider generating second and third internal clock signals based on the first internal clock signal and including an edge adjustor adjusting a timing of one of rising and falling edges of the third internal clock signal, an adjustment information holder supplying an edge adjustment signal to the edge adjustor, and a data strobe generator receiving the second and third internal clock signals to generate a first data strobe signal based on the second internal clock signal, and a second data strobe signal with a phase different from that of the first data strobe signal, based on the third internal clock signal. The edge adjustor adjusts the timing of at least one of the rising and falling edges of the third internal clock signal based on the edge adjustment signal.

Abstract: Power consumption in a DLL circuit having a DCC circuit is reduced. Specifically, a semiconductor circuit includes a change-in-duty detection circuit, activation and deactivation of which is controlled based upon a control signal (DCCEN), for comparing duty of a clock signal that has been generated based upon an input clock signal and a preset duty and outputting result of the comparison; and a duty determination circuit for outputting the control signal (DCCEN) for deactivating the change-in-duty detection circuit when the output of the change-in-duty detection circuit indicates that duty of the generated clock signal is in the vicinity of a target value, which is a preset duty, and outputting the control signal (DCCEN) for activating the change-in-duty detection circuit when the duty of the generated clock signal is not in the vicinity of the target value.

Abstract: A semiconductor device includes: a clock generator generating a first internal clock signal based on an external clock signal; a clock divider generating second and third internal clock signals based on the first internal clock signal and including an edge adjustor adjusting a timing of one of rising and falling edges of the third internal clock signal, an adjustment information holder supplying an edge adjustment signal to the edge adjustor, and a data strobe generator receiving the second and third internal clock signals to generate a first data strobe signal based on the second internal clock signal, and a second data strobe signal with a phase different from that of the first data strobe signal, based on the third internal clock signal. The edge adjustor adjusts the timing of at least one of the rising and falling edges of the third internal clock signal based on the edge adjustment signal.

Abstract: A clock control circuit includes: a phase determination circuit that generates a phase determination signal based on a phase of an external clock signal; a counter circuit having a count value updated based on a logic level of the phase determination signal; a delay line that generates an internal clock signal by delaying the external clock signal based on the count value; and a pitch adjustment circuit that sets an update pitch of the counter circuit to be twice as high as a minimum pitch in a period in which the phase determination signal has no change, and sets the update pitch of the counter circuit to the minimum pitch in response to a change in the phase determination signal. With this configuration, it is possible to realize quick and highly accurate locking of a DLL circuit.

Abstract: A DLL includes a first variable delay circuit that variably delays a first transition of an external signal, a second variable delay circuit that variably delays a second transition of the external signal, a synthesis circuit that synthesizes output signals of the first variable delay circuit and the second variable delay circuit, a duty change detection circuit that changes and detects the duty of an output signal of the synthesis circuit, and delay control circuits that vary the delay of the first variable delay circuit or the second variable delay circuit in accordance with the result of duty detection by the duty change detection circuit.

Abstract: A conduction member is used to connect in-chip equipotential pads 20 that have the same potential in a semiconductor device through PKG ball 10 arranged on the semiconductor device.

Abstract: A DLL (delay locked loop) circuit includes a first variable delay circuit, a pair of second variable delay circuits and a first synthesis circuit. The first variable delay circuit outputs signals of different delayed time values from each of first and second clock transitions. The pair of second variable delay circuits receive the signals from the first variable delay circuit, and the first synthesis circuit synthesizes output signals of the pair of second variable delay circuits to output the resulting synthesized signal. Each of the pair of second variable delay circuits includes a pair one-shot pulse generating circuits that generate one-shot pulses from the signals from the first variable delay circuit, a pair latch circuits, and a second synthesis circuit. The second synthesis circuit receives the set outputs of the latch circuits to output a signal which is a synthesis at a preset synthesis ratio.

Abstract: A semiconductor device has an output impedance adjustment circuit for automatically adjusting an output impedance of an output circuit including transistors connected in parallel. The output impedance adjustment circuit includes: a replica circuit including a circuit portion of the substantially same configuration as the output circuit; a comparator for comparing a magnitude of the output impedance of the replica circuit with a reference resistor and for outputting a comparison result as an internal counter control signal; a switching controller selectively switching between an external counter control signal from outside and the internal counter control signal; and a counter circuit for performing a count operation selectively according to the internal or the external counter control signal and for outputting a count value as an adjustment code which is supplied to the output circuit and the replica circuit so that each transistor is controlled to be on/off based on the adjustment code.

Abstract: A DLL circuit includes: a phase determining circuit that compares phases of respective rising edges of CK and LCLK to generate a determining signal R-U/D; a phase determining circuit that compares phases of respective falling edges of CK and LCLK to generate a determining signal F-U/D; a first adjusting circuit that adjusts a position of an active edge of LCLKR based on the determining signal R-U/D; a second adjusting circuit that adjusts a position of an active edge of LCLKF based on the determining signal F-U/D; a clock generating circuit that generates LCLK based on LCLKR and LCLKF; and a stop circuit that stops an adjusting operation by the second adjusting circuit in response to an adjusting direction of the active edge of LCLKR being opposite to each other to an adjusting direction of the active edge of LCLKF.

Abstract: A DLL includes a first variable delay circuit that variably delays a first transition of an external signal, a second variable delay circuit that variably delays a second transition of the external signal, a synthesis circuit that synthesizes output signals of the first variable delay circuit and the second variable delay circuit, a duty change detection circuit that changes and detects the duty of an output signal of the synthesis circuit, and delay control circuits that vary the delay of the first variable delay circuit or the second variable delay circuit in accordance with the result of duty detection by the duty change detection circuit.