Abstract: An epitaxial substrate for electronic devices is provided, which can improve vertical breakdown voltage and provides a method of producing the same. The epitaxial substrate includes a conductive SiC single crystal substrate, a buffer as an insulating layer on the SiC single crystal substrate, and a main laminate formed by epitaxially growing a plurality of Group III nitride layers on the buffer. Further, the buffer includes at least an initial growth layer in contact with the SiC single crystal substrate and a superlattice laminate having a superlattice multi-layer structure on the initial growth layer. The initial growth layer is made of a Ba1Alb1Gac1Ind1N material. Furthermore, the superlattice laminate is configured by alternately stacking a first layer made of a Ba2Alb2Gac2Ind2N material and a second layer made of a Ba3Alb3Gac3Ind3N material having a different band gap from the first layer.

Abstract: In a memory/logic conjugate system, a plurality of cluster memory chips each including a plurality of cluster memories (20) including basic cells (10) arranged in a cluster, the basic cell including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus (11) including a through-via, an arbitrary one of the basic cells is directly accessed through the multibus from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell is switched to a logic circuit as conjugate.

Abstract: A semiconductor material is provided comprising: a composition graded layer, formed on a Si substrate or an interlayer formed thereon, comprising a composition of AlXGa1-XN graded such that a content ratio of Al in the composition decreases continuously or discontinuously in a crystal growing direction; a superlattice composite layer, formed on the composition graded layer, comprising a high Al-containing layer comprising a composition of AlYGa1-YN and a low Al-containing layer comprising a composition of AlZGa1-ZN that are laminated alternately; and a nitride semiconductor layer formed on the superlattice composite layer.

Abstract: A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.

Abstract: An epitaxial substrate for electronic devices is provided, which can improve vertical breakdown voltage and provides a method of producing the same. The epitaxial substrate includes a conductive SiC single crystal substrate, a buffer as an insulating layer on the SiC single crystal substrate, and a main laminate formed by epitaxially growing a plurality of Group III nitride layers on the buffer. Further, the buffer includes at least an initial growth layer in contact with the SiC single crystal substrate and a superlattice laminate having a superlattice multi-layer structure on the initial growth layer. The initial growth layer is made of a Ba1Alb1Gac1Ind1N material. Furthermore, the superlattice laminate is configured by alternately stacking a first layer made of a Ba2Alb2Gac2Ind2N material and a second layer made of a Ba3Alb3Gac3Ind3N material having a different band gap from the first layer.

Abstract: There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.

Abstract: A semiconductor material is provided comprising: a composition graded layer, formed on a Si substrate or an interlayer formed thereon, comprising a composition of AlXGa1-XN graded such that a content ratio of Al in the composition decreases continuously or discontinuously in a crystal growing direction; a superlattice composite layer, formed on the composition graded layer, comprising a high Al-containing layer comprising a composition of AlYGa1-YN and a low Al-containing layer comprising a composition of AlZGa1-ZN that are laminated alternately; and a nitride semiconductor layer formed on the superlattice composite layer.

Abstract: The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection 20 for transmission of signals, a MOS capacitance element 10 having a gate electrode connected to the signal-transmission interconnection 20, a first voltage-applying interconnection 30 connected to a source and a drain of the MOS capacitance element 10 and applying a voltage to the source and the drain of the MOS capacitance element 10, a second voltage-applying interconnection 40 connected to a well of the MOS capacitance element 10, and applying a voltage to the well of said first MOS capacitance element 10.

Abstract: Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.

Abstract: The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection 20 for transmission of signals, a MOS capacitance element 10 having a gate electrode connected to the signal-transmission interconnection 20, a first voltage-applying interconnection 30 connected to a source and a drain of the MOS capacitance element 10 and applying a voltage to the source and the drain of the MOS capacitance element 10, a second voltage-applying interconnection 40 connected to a well of the MOS capacitance element 10, and applying a voltage to the well of said first MOS capacitance element 10.

Abstract: Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.

Abstract: A ceramic heater includes a cylindrical member; a ceramic heating member, which is disposed within the cylindrical member such that an end portion thereof is projected from an end of the cylindrical member; and a metallic shell, which surrounds the cylindrical member. The ceramic heating member includes a ceramic body and a U-shaped conductive ceramic element, which is embedded in an end portion of the ceramic body. A direction-changing portion of the conductive ceramic element generates heat through electrical resistance when electricity is supplied to the conductive ceramic element through electrodes connected to the end portions of the conductive ceramic element. The electrodes are disposed such that the distance L between the ends of the electrodes and the end of the metallic shell satisfies the expression L≦1 mm, where the distance L is considered negative when the ends of the electrodes are located within the metallic shell.

Abstract: A phase adjusting circuit for adjusting phases of output powers from two high frequency power generators in a plasma processing apparatus comprises first and second synthesizing circuits for generating first and second high frequency signals of a predetermined waveform with frequencies of f0 and f0.+-..DELTA.f (.DELTA.f<<f0), a phase difference detection circuit for detecting a phase difference between detection signals of plate electrodes, a third waveform synthesizing circuit for generating a high frequency signal with frequency and waveform same as the first frequency signal which has a phase determined from a phase error between a set phase difference and an output from the phase difference detection circuit and a phase adjusting circuit which determines output powers of the two high frequency power generators base on outputs of the first and third waveform synthesizing circuits.

Abstract: A sliding bearing and a crankshaft used for a crankshaft-connecting rod assembly are disclosed. Particularly, the invention concerns a sliding bearing for a crankshaft-connecting rod assembly, in which journal sections are each provided at each end of at least one crankshaft, one of said journal sections is rotatably supported so that said crankshaft is rotated about said one journal section, a connecting rod has one end rotatably coupled to said other journal section, and a lubricant is supplied form an oil port of each said journal section.

Abstract: An A/D converter apparatus comprises: a sampling signal generating means to generate an oversampling signal and an internal sampling signal; a converter means to convert an input analog signal into a digital signal in synchronism with the oversampling signal; and a decimator means to perform a specified decimation on the digital signal in synchronism with the internal sampling signal; whereby the sampling signal generating means maintains the frequencies of the oversampling signal and the internal sampling signal in a specified relationship.

Abstract: A method of making a ceramic heater by preparing a heating coil having a circular cross-section and bending it into a U-shaped form. Lead wires are connected to the ends of the U-shaped coil; the coil is embedded in a ceramic powder to form a preform having a substantially rectangular cross-section. The preform is compacted under heat to reduce the length of the rectangular cross-section and deform the coil embedded therein into a coil having an oval cross-section. The preform is sintered to form a ceramic product having a substantially circular cross-section and then ground to form a product having a circular cross-section.

Abstract: A ceramic heater including a ceramic insulator having a circular cross section, and a heating coil having an oval cross section, embedded in the insulator along the length thereof, and bent in a U-shaped form with the bend adjacent one end of the insulator. One of a pair of parallel coil portions defining the U-shaped coil has a long cross sectional diameter lying parallel to that of the other coil portion. The diameter of a cylinder defined by the outer surfaces of the coil portions and the outside diameter of the insulator have a ratio of 35:100 to 70:100.

Abstract: A nickel alloy for spark plug electrodes consisting essentially of, by weight percent,about 0.2 to 3% Siabout 0.5% Mn or lessat least two metals selected from the group consisting ofabout 0.2 to 3% Crabout 0.2 to 3% Al andabout 0.01 to 1% Yand the balance nickel.

Abstract: The present invention relates to a transistor circuit, and more specifically to a static decoder circuit made up of a series circuit of a NOR logic gate circuit consisting of a plurality of MISFET's for receiving address signals through the gates, an inverter circuit for receiving the output of the logic gate circuit through the gate, a first MISFET for receiving the output of the logic gate circuit through the gate, and a second MISFET for receiving the output of the inverter circuit through the gate, wherein said NOR logic gate circuit and inverter circuit are connected to a ground terminal via a first switching MISFET which receives the control signals through the gate, and said series circuit is connected to a power supply terminal via a second switching MISFET which receives the control signals through the gate.

Abstract: A potential setting circuit is connected with a pair of common data lines which are made operative to receive data signals from memory cells. The potentials at the paired common data lines, which are forcibly set by the potential setting circuit, are set substantially at the middle level between the high and low levels of the data signals which are generated from the memory cells. As a result, the potential at the paired common data lines are changed within a relatively short time to the level of the data signals generated from the memory cells.