Patents by Inventor Tsuneo Ito

Tsuneo Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10840261
    Abstract: A semiconductor storage device includes a base portion, a stacked body, and a first column. The base portion includes a substrate, a semiconductor element on the substrate, lower-layer wiring above the semiconductor element, and a first conductive layer above the lower-layer wiring and made of a metal compound or polycrystal silicon. The stacked body is above the first conductive layer. The stacked body includes second conductive layers and insulating films stacked alternately. The first column includes a semiconductor body and a memory film. The semiconductor body extends in a stacked direction of the stacked body and is electrically connected to the first conductive layer. A memory film has a charge trap between the plurality of second conductive layers and the semiconductor body. The first conductive layer is provided between the stacked body and the lower-layer wiring, and between a peripheral region of the stacked body and the lower-layer wiring.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takamasa Ito, Ken Komiya, Tsuneo Uenaka
  • Publication number: 20200247747
    Abstract: The present invention provides a heterocyclic compound having an orexin type 2 receptor agonist activity. A compound represented by the formula (I): wherein each symbol is as described in the specification, or a salt thereof has an orexin type 2 receptor agonist activity, and is useful as an agent for the prophylaxis or treatment of narcolepsy.
    Type: Application
    Filed: January 30, 2020
    Publication date: August 6, 2020
    Applicant: Takeda Pharmaceutical Company Limited
    Inventors: Yasushi Hattori, Yuhei Miyanohana, Yuichi Kajita, Tatsuki Koike, Yasutaka Hoashi, Norihito Tokunaga, Alexander Martin Pawliczek, Tsuneo Oda, Tohru Miyazaki, Yoshiteru Ito, Kohei Takeuchi, Keisuke Imamura, Takahiro Sugimoto
  • Publication number: 20200207715
    Abstract: The present invention provides a heterocyclic compound having an orexin type 2 receptor agonist activity. A compound represented by the formula (I): wherein each symbol is as described in the specification, or a salt thereof, is useful as an agent for the prophylaxis or treatment of narcolepsy.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Applicant: Takeda Pharmaceutical Company Limited
    Inventors: Yuichi Kajita, Yuhei MIYANOHANA, Tatsuki KOIKE, Kohei TAKEUCHI, Yoshiteru ITO, Norihito TOKUNAGA, Takahiro SUGIMOTO, Tohru MIYAZAKI, Tsuneo ODA, Yasutaka HOASHI, Yasushi HATTORI, Keisuke IMAMURA
  • Publication number: 20200207734
    Abstract: The present invention provides a heterocyclic compound having an orexin type 2 receptor agonist activity. A compound represented by the formula (I): wherein each symbol is as described in the specification, or a salt thereof, is useful as an agent for the prophylaxis or treatment of narcolepsy.
    Type: Application
    Filed: August 2, 2018
    Publication date: July 2, 2020
    Applicant: Takeda Pharmaceutical Company Limited
    Inventors: Yuichi KAJITA, Satoshi MIKAMI, Yuhei MIYANOHANA, Tatsuki KOIKE, Masaki DAINI, Norio OYABU, Masaki OGINO, Kohei TAKEUCHI, Yoshiteru ITO, Norihito TOKUNAGA, Takahiro SUGIMOTO, Tohru MIYAZAKI, Tsuneo ODA, Yasutaka HOASHI, Yasushi HATTORI, Keisuke IMAMURA
  • Patent number: 10584097
    Abstract: The present invention provides a heterocyclic compound having an orexin type 2 receptor agonist activity. A compound represented by the formula (I): wherein each symbol is as described in the specification, or a salt thereof, is useful as an agent for the prophylaxis or treatment of narcolepsy.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: March 10, 2020
    Assignee: Takeda Pharmaceutical Company Limited
    Inventors: Yuichi Kajita, Yuhei Miyanohana, Tatsuki Koike, Kohei Takeuchi, Yoshiteru Ito, Norihito Tokunaga, Takahiro Sugimoto, Tohru Miyazaki, Tsuneo Oda, Yasutaka Hoashi, Yasushi Hattori, Keisuke Imamura
  • Publication number: 20200075623
    Abstract: A semiconductor storage device includes a base portion, a stacked body, and a first column. The base portion includes a substrate, a semiconductor element on the substrate, lower-layer wiring above the semiconductor element, and a first conductive layer above the lower-layer wiring and made of a metal compound or polycrystal silicon. The stacked body is above the first conductive layer. The stacked body includes second conductive layers and insulating films stacked alternately. The first column includes a semiconductor body and a memory film. The semiconductor body extends in a stacked direction of the stacked body and is electrically connected to the first conductive layer. A memory film has a charge trap between the plurality of second conductive layers and the semiconductor body. The first conductive layer is provided between the stacked body and the lower-layer wiring, and between a peripheral region of the stacked body and the lower-layer wiring.
    Type: Application
    Filed: February 26, 2019
    Publication date: March 5, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takamasa ITO, Ken Komiya, Tsuneo Uenaka
  • Publication number: 20200017444
    Abstract: The present invention provides a heterocyclic compound having an orexin type 2 receptor agonist activity. A compound represented by the formula (I): wherein each symbol is as described in the specification, or a salt thereof, is useful as an agent for the prophylaxis or treatment of narcolepsy.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 16, 2020
    Applicant: Takeda Pharmaceutical Company Limited
    Inventors: Yuichi KAJITA, Satoshi MIKAMI, Yuhei MIYANOHANA, Tatsuki KOIKE, Masaki DAINI, Norio OYABU, Masaki OGINO, Kohei TAKEUCHI, Yoshiteru ITO, Norihito TOKUNAGA, Takahiro SUGIMOTO, Tohru MIYAZAKI, Tsuneo ODA, Yasutaka HOASHI, Yasushi HATTORI, Keisuke IMAMURA
  • Patent number: 10428023
    Abstract: The present invention provides a heterocyclic compound having an orexin type 2 receptor agonist activity. A compound represented by the formula (I): wherein each symbol is as described in the specification, or a salt thereof, is useful as an agent for the prophylaxis or treatment of narcolepsy.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 1, 2019
    Assignee: Takeda Pharmaceutical Company Limited
    Inventors: Yuichi Kajita, Yuhei Miyanohana, Tatsuki Koike, Kohei Takeuchi, Yoshiteru Ito, Norihito Tokunaga, Takahiro Sugimoto, Tohru Miyazaki, Tsuneo Oda, Yasutaka Hoashi, Yasushi Hattori, Keisuke Imamura
  • Patent number: 10427981
    Abstract: A piezoelectric material contains: a first component which is a rhombohedral crystal in a single composition, has a Curie temperature Tc1, and is a lead-free-system composite oxide having a perovskite-type structure; a second component which is a crystal other than the rhombohedral crystal in a single composition, has a Curie temperature Tc2<Tc1, and is a lead-free-system composite oxide having a perovskite-type structure; and a third component which is a crystal other than the rhombohedral crystal in a single composition similar to the second component, has a Curie temperature Tc3?Tc1, and is a lead-free-system composite oxide that has a perovskite-type structure and is different from the second component. When a molar ratio of the third component to the sum of the second component and the third component is ? and ?×Tc3+(1??)×Tc2 is Tc4, |Tc4?Tc2|?50° C.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: October 1, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Koji Sumi, Kazuya Kitada, Tomohiro Sakai, Yasuaki Hamada, Tetsuya Isshiki, Satoshi Kimura, Akio Ito, Tsuneo Handa
  • Patent number: 8426893
    Abstract: An epitaxial substrate for electronic devices is provided, which can improve vertical breakdown voltage and provides a method of producing the same. The epitaxial substrate includes a conductive SiC single crystal substrate, a buffer as an insulating layer on the SiC single crystal substrate, and a main laminate formed by epitaxially growing a plurality of Group III nitride layers on the buffer. Further, the buffer includes at least an initial growth layer in contact with the SiC single crystal substrate and a superlattice laminate having a superlattice multi-layer structure on the initial growth layer. The initial growth layer is made of a Ba1Alb1Gac1Ind1N material. Furthermore, the superlattice laminate is configured by alternately stacking a first layer made of a Ba2Alb2Gac2Ind2N material and a second layer made of a Ba3Alb3Gac3Ind3N material having a different band gap from the first layer.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: April 23, 2013
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Jo Shimizu, Tomohiko Shibata, Ryo Sakamoto, Tsuneo Ito
  • Publication number: 20130061004
    Abstract: In a memory/logic conjugate system, a plurality of cluster memory chips each including a plurality of cluster memories (20) including basic cells (10) arranged in a cluster, the basic cell including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus (11) including a through-via, an arbitrary one of the basic cells is directly accessed through the multibus from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell is switched to a logic circuit as conjugate.
    Type: Application
    Filed: October 4, 2012
    Publication date: March 7, 2013
    Inventors: Kanji OTSUKA, Tsuneo ITO, Yoichi SATO, Masahiro YOSHIDA, Shigeru YAMAMOTO, Takeshi KOYAMA, Yuko TANBA, Yutaka AKIYAMA
  • Patent number: 8344356
    Abstract: A semiconductor material is provided comprising: a composition graded layer, formed on a Si substrate or an interlayer formed thereon, comprising a composition of AlXGa1-XN graded such that a content ratio of Al in the composition decreases continuously or discontinuously in a crystal growing direction; a superlattice composite layer, formed on the composition graded layer, comprising a high Al-containing layer comprising a composition of AlYGa1-YN and a low Al-containing layer comprising a composition of AlZGa1-ZN that are laminated alternately; and a nitride semiconductor layer formed on the superlattice composite layer.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: January 1, 2013
    Assignees: Dowa Electronics Materials Co., Ltd., National University Corporation Nagoya Institute of Technology
    Inventors: Ryo Sakamoto, Jo Shimizu, Tsuneo Ito, Takashi Egawa
  • Patent number: 8305789
    Abstract: A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: November 6, 2012
    Inventors: Kanji Otsuka, Tsuneo Ito, Yoichi Sato, Masahiro Yoshida, Shigeru Yamamoto, Takeshi Koyama, Yuko Tanba, Yutaka Akiyama
  • Publication number: 20120091435
    Abstract: An epitaxial substrate for electronic devices is provided, which can improve vertical breakdown voltage and provides a method of producing the same. The epitaxial substrate includes a conductive SiC single crystal substrate, a buffer as an insulating layer on the SiC single crystal substrate, and a main laminate formed by epitaxially growing a plurality of Group III nitride layers on the buffer. Further, the buffer includes at least an initial growth layer in contact with the SiC single crystal substrate and a superlattice laminate having a superlattice multi-layer structure on the initial growth layer. The initial growth layer is made of a Ba1Alb1Gac1Ind1N material. Furthermore, the superlattice laminate is configured by alternately stacking a first layer made of a Ba2Alb2Gac2Ind2N material and a second layer made of a Ba3Alb3Gac3Ind3N material having a different band gap from the first layer.
    Type: Application
    Filed: May 10, 2010
    Publication date: April 19, 2012
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya Ikuta, Jo Shimizu, Tomohiko Shibata, Ryo Sakamoto, Tsuneo Ito
  • Publication number: 20110255323
    Abstract: There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.
    Type: Application
    Filed: December 23, 2010
    Publication date: October 20, 2011
    Inventors: Kanji Otsuka, Tsuneo Ito, Yoichi Sato, Masahiro Yoshida, Shigeru Yamamoto, Takeshi Koyama, Yuko Tanba, Yutaka Akiyama
  • Publication number: 20110001127
    Abstract: A semiconductor material is provided comprising: a composition graded layer, formed on a Si substrate or an interlayer formed thereon, comprising a composition of AlXGa1-XN graded such that a content ratio of Al in the composition decreases continuously or discontinuously in a crystal growing direction; a superlattice composite layer, formed on the composition graded layer, comprising a high Al-containing layer comprising a composition of AlYGa1-YN and a low Al-containing layer comprising a composition of AlZGa1-ZN that are laminated alternately; and a nitride semiconductor layer formed on the superlattice composite layer.
    Type: Application
    Filed: December 17, 2008
    Publication date: January 6, 2011
    Applicants: DOWA ELECTRONICS MATERIALS CO., LTD., NATIONAL UNIVERSITY CORPORATION NAGOYA INSTITUTE OF TECHNOLOGY
    Inventors: Ryo Sakamoto, Jo Shimizu, Tsuneo Ito, Takashi Egawa
  • Patent number: 7804111
    Abstract: The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection 20 for transmission of signals, a MOS capacitance element 10 having a gate electrode connected to the signal-transmission interconnection 20, a first voltage-applying interconnection 30 connected to a source and a drain of the MOS capacitance element 10 and applying a voltage to the source and the drain of the MOS capacitance element 10, a second voltage-applying interconnection 40 connected to a well of the MOS capacitance element 10, and applying a voltage to the well of said first MOS capacitance element 10.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: September 28, 2010
    Assignee: Tama-TLO Ltd.
    Inventors: Kanji Otsuka, Munekazu Takano, Fumio Mizuno, Saburo Yokokura, Tsuneo Ito, Yuko Tanba, Yutaka Akiyama
  • Patent number: 7791852
    Abstract: Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: September 7, 2010
    Assignees: Fujitsu Microelectronics Limited, OKI Semiconductor Co., Ltd., Kyocera Corporation, Kabushiki Kaisha Toshiba, Fuji Xerox Co., Ltd., Renesas Technology Corp
    Inventors: Kanji Otsuka, Tamotsu Usami, Yutaka Akiyama, Tsuneo Ito, Yuko Tanba
  • Publication number: 20090108955
    Abstract: The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection 20 for transmission of signals, a MOS capacitance element 10 having a gate electrode connected to the signal-transmission interconnection 20, a first voltage-applying interconnection 30 connected to a source and a drain of the MOS capacitance element 10 and applying a voltage to the source and the drain of the MOS capacitance element 10, a second voltage-applying interconnection 40 connected to a well of the MOS capacitance element 10, and applying a voltage to the well of said first MOS capacitance element 10.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 30, 2009
    Inventors: Kanji Otsuka, Munekazu Takano, Fumio Mizuno, Saburo Yokokura, Tsuneo Ito, Yuko Tanba, Yutaka Akiyama
  • Publication number: 20080042686
    Abstract: Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.
    Type: Application
    Filed: June 28, 2007
    Publication date: February 21, 2008
    Inventors: Kanji Otsuka, Tamotsu Usami, Yutaka Akiyama, Tsuneo Ito, Yuko Tanba