Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a series of sensing operations respectively corresponding to a plurality of sensing voltages, wherein a sensing voltage of a specific sensing operation of the series of sensing operations has a sensing voltage determined according to a result of an initial sensing operation of the series of sensing operations; determining a threshold voltage of the Flash cell according to at least a digital value generated by the series of sensing operations; and using the determined threshold voltage to perform soft decoding of the Flash cell.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read the first logical page to obtain first readout information, second readout information and third readout information, respectively; selecting a second logical page of the physical page; using a second set of threshold voltage to read the second logical page to generate fourth readout information; adjusting the first set of threshold voltages to generate an adjusted first set of threshold voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information; and using the adjusted first set of threshold voltages to read the first logical page of the flash memory module.

Abstract: A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.

Abstract: A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.

Abstract: A flash memory controller, to be coupled between a host and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host to form a super block stored within the flash memory module, to generate wordline-dimensional check code data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional check code data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional check code data and the finger-dimensional check code data so as to obtain correct data content of the specific data.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read a first logical page of a physical page of the flash memory module to obtain first readout information, second readout information and third readout information, respectively; decoding the first readout information, the second readout information and the third readout information to generate decoded data of the first logical page; and generating a LLR mapping table according to the decode data of the first logical page, the first readout information, the second readout information and the third readout information, for use when reading and decoding other logical pages.

Abstract: A control method of a memory device includes: reading and decoding first data of a first chunk, wherein the first chunk is located in a first data page of a super data page, and the super data page includes multiple data pages respectively located in multiple data planes; in response to the first chunk failing to be decoded, obtaining data of multiple corresponding chunks of the first chunk, wherein the multiple corresponding chunks are located in other data pages of the super data page; and in response to all of the data in the multiple corresponding chunks not being successfully decoded, determining whether to give up the decoding operation of the first chunk according to a symptom weight of the first chunk and at least one symptom weight of at least one corresponding chunk.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: The present invention provides a control method of the memory device. In the operation of the memory device, the soft information is compressed by a control circuit within the flash memory module, so that the second readout information including the compressed soft information transmitted by the flash memory module has much smaller data size. Therefore, the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

Abstract: A data programming method for a flash memory includes: writing a write data to a page buffer of the flash memory; encoding the write data to generate first parity data corresponding to the write data, and writing the first parity data to the page buffer; while generating the first parity data, performing an error detection based on the write data and the first parity data to produce an error detection result; and when the error detection result indicates that there is no error in the first parity data, issuing a program command to the flash memory to program the write data and the first parity data in the page buffer into a flash memory element of the flash memory.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: The invention provides a method for accessing a flash memory module, wherein the method includes the steps of: classifying multiple read retry tables into at least a first group and a second group to establish a classifying and sorting table, wherein each of the multiple read retry tables records at least one reading voltage, and any two read retry tables do not have exactly the same reading voltage; selecting a first read retry table from the first group to read a page of a block of the flash memory module to generate first read data; and when a decoder fails to decode the first read data, selecting a second read retry table from the first group to read the page of the block of the flash memory module to generate second read data for the decoder to decode.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: The present invention provides a control method of the memory device. In the operation of the memory device, the soft information is compressed by a control circuit within the flash memory module, so that the second readout information including the compressed soft information transmitted by the flash memory module has much smaller data size. Therefore, the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the flash memory module includes a plurality of blocks. The control method includes the steps of: obtaining a read count of a specific block; obtaining a time stamp of the specific block, wherein the time stamp is a write time of the specific block; calculating a time difference between a current system time and the time stamp of the specific block; and using the read count of the specific block and the time difference, and referring to a read count and threshold time mapping table to determine whether to arrange the specific block in a garbage collection pool.