Abstract: The present invention provides a control method of the memory device. In the operation of the memory device, the soft information is compressed by a control circuit within the flash memory module, so that the second readout information including the compressed soft information transmitted by the flash memory module has much smaller data size. Therefore, the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

Abstract: A data programming method for a flash memory includes: writing a write data to a page buffer of the flash memory; encoding the write data to generate first parity data corresponding to the write data, and writing the first parity data to the page buffer; while generating the first parity data, performing an error detection based on the write data and the first parity data to produce an error detection result; and when the error detection result indicates that there is no error in the first parity data, issuing a program command to the flash memory to program the write data and the first parity data in the page buffer into a flash memory element of the flash memory.

Abstract: A polishing apparatus for double-sided polishing of semiconductor wafers including a first platen, a second platen, a wafer carrier, and a controller is disclosed. The controller is configured to perform operations including determining whether a batch of the semiconductor wafers is loaded on the wafer carrier for double-sided polishing and retrieving specification for the batch of semiconductor wafers. The operations include based on the retrieved specification, determining an amount of tuning required for one or more flatness control parameters, and based on the amount of tuning required for the one or more flatness control parameters, identifying, or generating a recipe to perform the double-sided polishing on the batch of the semiconductor wafers. The operations include storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the double-sided polishing on the batch of the semiconductor wafers.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: A method for establishing a disease prediction model is provided. The method includes the steps of extracting feature values for multiple microbiota features from microbiota data of each of a plurality of samples, selecting a portion of the extracted microbiota features as selected features, and training a disease prediction model. Each piece of training data used in training the disease prediction model includes (i) disease data for each of the samples and (ii) the feature values of the selected features for the sample. The microbiota features include species-level features, microbiota interaction features, and community-level features.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: The invention provides a method for accessing a flash memory module, wherein the method includes the steps of: classifying multiple read retry tables into at least a first group and a second group to establish a classifying and sorting table, wherein each of the multiple read retry tables records at least one reading voltage, and any two read retry tables do not have exactly the same reading voltage; selecting a first read retry table from the first group to read a page of a block of the flash memory module to generate first read data; and when a decoder fails to decode the first read data, selecting a second read retry table from the first group to read the page of the block of the flash memory module to generate second read data for the decoder to decode.

Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: A method for puffing natural cheese includes the following steps of: step 1: subjecting a natural cheese to a physical pretreatment to form a target shape; step 2: placing the natural cheese after physical pretreatment into a bearing plate; step 3: sending the natural cheese placed in the bearing plate into a puffing cavity of a puffing equipment; step 4: setting multiple puffing process parameters for the puffing equipment; step 5: providing an electromagnetic energy by the puffing equipment to perform a puffing process on the natural cheese; and step 6: producing a puffed product after the puffing process is completed. A puffed product of natural cheese uses the process disclosed above. The technology of the method and the puffed product has great market potential for the puffed food production of natural cheese.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the flash memory module includes a plurality of blocks. The control method includes the steps of: obtaining a read count of a specific block; obtaining a time stamp of the specific block, wherein the time stamp is a write time of the specific block; calculating a time difference between a current system time and the time stamp of the specific block; and using the read count of the specific block and the time difference, and referring to a read count and threshold time mapping table to determine whether to arrange the specific block in a garbage collection pool.

Abstract: The present invention provides a control method of the memory device. In the operation of the memory device, the soft information is compressed by a control circuit within the flash memory module, so that the second readout information including the compressed soft information transmitted by the flash memory module has much smaller data size. Therefore, the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

Abstract: A first conductive pad disposed over a first side of a substrate in a first direction. A second conductive pad is disposed over a second side of the substrate in the first direction. A through-substrate via (TSV) extends into the substrate in the first direction. The TSV is disposed between the first conductive pad and the second conductive pad in the first direction. An air liner disposed between the TSV and the substrate in a second direction different from the first direction.

Abstract: A light-emitting device is provided. The light-emitting device generates a white light and includes at least one light-emitting diode. The at least one light-emitting diode generates a light beam with a broadband blue spectrum and includes a first semiconductor layer, a second semiconductor layer and a multiple quantum well structure. The multiple quantum well structure is located between the first semiconductor layer and the second semiconductor layer, and includes well layers and barrier layers. The well layers include a first well layer, a second well layer and third well layers different in indium concentrations. The first well layer has the largest indium concentration, and the third well layers have the smallest indium concentration. Three of the well layers that are closest to the first semiconductor layer are the third well layers, and the first well layer is closer to the second semiconductor layer than the first semiconductor layer.

Abstract: Embodiments of the present disclosure relate to methods for warpage correction. Particularly, embodiments of the present disclosure relate to substrate level warpage correction by depositing one or more warpage correction layers in a redistribution layer (RDL) structure, a front side warpage correction layer, and/or a back side warpage correction layer. In some embodiments, the warpage correction layer is a high stress dielectric layer. Characteristics of the warpage correction layer, such as stress level, and thickness, may be determined according to the substrate level warpage and the die level packaging scheme using an auto process control program.

Abstract: The present invention discloses an automatic signal deployer, a signal deployment system, an automatic signal path deployment method, and a behavior control signal generation method of a deployment agent. The signal deployment system includes an automatic signal deployer, a deployment agent and a base station. The deployment agent receives signal quality data, generates a behavior control signal according to the signal quality data, and sends out the behavior control signal to the automatic signal deployer. The automatic signal deployer receives the behavior control signal and a source signal coming from the base station, performs deployment according to the behavior control signal, whereby the automatic signal deployer can transmit the source signal toward a signal path allocation direction and complete automatic deployment of signal paths.

Abstract: A data recovery method for a flash memory includes: during a first programming pass, programming a memory cell of the flash memory to a specific charge state, thereby to store middle page data and lower page data into the memory cell; reading the memory cell to back up one of the middle page data and the lower page data stored in the memory cell to another memory cell in the flash memory; upon detecting an error during or after a second programming pass, based on a current voltage of the memory cell and the backed-up one of the middle page data and the lower page data from the another memory cell of the flash memory, recovering the middle page data and the lower page data of the memory cell; and writing back the recovered middle page data and the recovered lower page data to the flash memory.