Patents by Inventor Tsung-Chieh Yang

Tsung-Chieh Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220202990
    Abstract: A tissue scaffold for use in a tendon and/or ligament is provided, which includes a weave formed by interlacing warp yarns and weft yarns, wherein the warp yarns include a plurality of fibers with an alternative shaped cross section structure, and the weave includes: a main body area with a bioactive component formed on the fiber surface, and a fixed area comprises the weft yarn having a bioceramic material. The tissue scaffold prepared in the present disclosure has the characteristics of stimulating the growth of tissues and inducing tissue repair, effectively improving the ability of tissue regeneration and bone healing, and is beneficial to the reconstruction of the tendon and/or ligament.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: Hsin-Hsin Shen, Pei-I Tsai, Chih-Chieh Huang, Chien-Cheng Tai, Yi-Hung Wen, Jeng-Liang Kuo, Chun-Hsien Ma, Lih-Tao Hsu, Shin-I Huang, Kuo-Yi Yang, Tsung-Hsien Wu
  • Publication number: 20220208383
    Abstract: A method and a system for mental index prediction are provided. The method includes the following steps. A plurality of images of a subject person are obtained. A plurality of emotion tags of the subject person in the images are analyzed. A plurality of integrated emotion tags in a plurality of predetermined time periods are calculated according to the emotion tags respectively corresponding to the images. A plurality of preferred features are determined according to the integrated emotion tags. A mental index prediction model is established according to the preferred features to predict a mental index according to the emotional index prediction model.
    Type: Application
    Filed: July 2, 2021
    Publication date: June 30, 2022
    Applicants: Acer Incorporated, National Yang Ming Chiao Tung University
    Inventors: Chun-Hsien Li, Szu-Chieh Wang, Andy Ho, Liang-Kung Chen, Jun-Hong Chen, Li-Ning Peng, Tsung-Han Yang, Yun-Hsuan Chan, Tsung-Hsien Tsai
  • Patent number: 11373723
    Abstract: The present invention provides an encoder built-in self-test (BIST) circuit applied in a flash memory controller, wherein the encoder BIST circuit includes a control circuit and an encoder. In operations of the encoder BIST circuit, without accessing any flash memory, the control circuit generates input data to the encoder, and the encoder encodes the input data to generate a check code to the control circuit, wherein the check code is arranged to determine whether functions of the encoder fail or not.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: June 28, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 11372718
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the method comprises: receiving data and a corresponding metadata from a host device; performing a CRC operation upon the data to generate a CRC code; encoding the metadata and the CRC code to generate an adjusted parity code; encoding the data and the adjusted parity code to generate encoded data, wherein the encoded data comprises the data, the adjusted parity code and an error correction code corresponding to the data and the adjusted parity code; and writing the encoded data and the metadata to a page of a block of a flash memory module.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 28, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 11372592
    Abstract: The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 28, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 11366616
    Abstract: A method for performing storage control in a storage server may include: regarding any memory device of a plurality of memory devices installed at the storage server, assigning a channel of multiple channels within the memory device for access control corresponding to a thread of a plurality of threads running on the storage server, wherein the storage server configures the plurality of memory devices to form a RAID of the storage server; and during storing a series of logical access units (LAUs) into the RAID, writing information into respective sets of pages of the plurality of memory devices as pages in a LAU of the series of LAUs according to a predetermined arrangement rule, to make the respective sets of pages be sequentially written into the plurality of memory devices respectively with aid of the assignment of the channel of the multiple channels to the thread. Associated apparatus are provided.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: June 21, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20220182074
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 11354231
    Abstract: A method for performing access management of a memory device with aid of information arrangement and associated apparatus (e.g. the memory device and controller thereof, and an associated electronic device) are provided. The method may include: when the host device sends a write command to the memory device, utilizing the memory controller to generate a plurality of ECC chunks respectively corresponding to a plurality of sets of memory cells of the NV memory according to data, for establishing one-to-one mapping between the plurality of ECC chunks and the plurality of sets of memory cells; and utilizing the memory controller to store the plurality of ECC chunks into the plurality of sets of memory cells, respectively, to prevent any two ECC chunks of the ECC chunks from sharing a same set of memory cells of the sets of memory cells, to enhance read performance of the memory controller regarding the data.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 7, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20220158026
    Abstract: A light-emitting diode is provided. The light-emitting diode includes a P-type semiconductor layer, a N-type semiconductor layer, and a light-emitting stack located therebetween. The light-emitting stack includes a plurality of well layers and a plurality of barrier layers that are alternately stacked, the well layers includes at least one first well layer, at least one second well layer, and third well layers that have different indium concentrations. The first well layer has the largest indium concentration, and the third well layers have the smallest indium concentration. Three of well layers that are closest to the P-type semiconductor layer are the third well layers, and the first well layer is closer to the N-type semiconductor layer than the P-type semiconductor layer.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Inventors: BEN-JIE FAN, JING-QIONG ZHANG, YI-QUN LI, HUNG-CHIH YANG, TSUNG-CHIEH LIN, HO-CHIEN CHEN, SHUEN-TA TENG, CHENG-CHANG HSIEH
  • Patent number: 11331762
    Abstract: A method for synchronous control of a gantry mechanism with online inertia matching is applicable to a machine tool equipped with a gantry mechanism. The gantry mechanism includes two rails, a crossbeam and a saddle, in which the saddle is disposed on the crossbeam, and the crossbeam is disposed by crossing the two rails. Each of the two rails is furnished with a driving apparatus for synchronously driving the crossbeam, and the driving apparatus includes a drive motor and a lead screw. This method includes the steps of: obtaining gantry-mechanism information; detecting position information of the saddle on the crossbeam; evaluating the position information and the gantry-mechanism information to derive load-inertia variety information; and, evaluating the load-inertia variety information to adjust torque-output information of the drive motor corresponding to the respective driving apparatus.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 17, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Min-Rong Chen, Shih-Chang Liang, Tsung-Yu Yang, Jun-Hong Guo, Jih-Chieh Lee
  • Patent number: 11323133
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 3, 2022
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Publication number: 20220093191
    Abstract: The present invention provides a method for access a flash memory module, wherein the method includes the steps of: sending a read command to the flash memory module to read a plurality of memory cells of at least one word line of the flash memory module by using a plurality of read voltages, wherein each memory cell is configured to store a plurality of bits, each memory cell has a plurality of states, the states are used to indicate different combinations of the plurality of bits; obtaining readout information from the flash memory module; analyzing the readout information to determine numbers of the states of the memory cells; determining if the memory cells are balance or unbalance according the numbers of the states of the memory cells to generate a determination result; and referring to the determination result to adjust voltage levels of the plurality of read voltages.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventor: Tsung-Chieh Yang
  • Publication number: 20220066641
    Abstract: A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 3, 2022
    Applicant: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang
  • Patent number: 11256435
    Abstract: A method for performing data-accessing management in a storage server and associated apparatus such as a host device, a storage device, etc. are provided. The method includes: in response to a client request of writing a first set of data into the storage server, utilizing the host device within the storage server to trigger broadcasting an internal request corresponding to the client request toward each storage device of a plurality of storage devices within the storage server; and in response to the internal request corresponding to the client request, utilizing said each storage device of the plurality of storage devices to search for the first set of data in said each storage device to determine whether the first set of data has been stored in any storage device, for controlling the storage server completing the client request without duplication of the first set of data within the storage server.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: February 22, 2022
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Wen-Long Wang
  • Patent number: 11256425
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method includes the steps of: sending a read command to the flash memory module to ask for data on at least one memory unit; receiving multi-bit information of a plurality of memory cells of the at least one memory unit from the flash memory module; and analyzing the multi-bit information of the plurality of memory cells to obtain a threshold voltage distribution of the plurality of memory cells for determining a decoding process.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: February 22, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20210406119
    Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.
    Type: Application
    Filed: September 8, 2021
    Publication date: December 30, 2021
    Applicant: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 11210209
    Abstract: The present invention provides a method for managing a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the method includes the steps of: using a time management circuit to generate current time information; when data is written into any one of the blocks, recording the time information generated by the time management circuit; and determining at least one specific block according to quantity of invalid pages within each block and the time information of each block.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 28, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Pi-Ju Tsai, Tsung-Chieh Yang
  • Patent number: 11209984
    Abstract: A method for performing data-compression management in a storage server may include: receiving data from a host device; performing entropy detection on a plurality of sets of partial data to generate entropy detection values of the plurality of sets of partial data, respectively; classifying the plurality of sets of partial data according to the entropy detection values of the plurality of sets of partial data, respectively, to perform data compression on at least one portion of the plurality of sets of partial data through a plurality of data compression modules, respectively, wherein the plurality of data compression modules correspond to different compression capabilities, respectively; and storing the plurality of sets of partial data into at least one storage device of the storage server and recording address mapping information of the plurality of sets of partial data, respectively. An associated apparatus is also provided.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: December 28, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Wen-Long Wang
  • Publication number: 20210398596
    Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 23, 2021
    Applicant: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 11175841
    Abstract: A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 16, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang