Patents by Inventor Tsung-Chieh Yang

Tsung-Chieh Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190220353
    Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 10348332
    Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
    Type: Grant
    Filed: September 16, 2018
    Date of Patent: July 9, 2019
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 10324789
    Abstract: A method for accessing a flash memory module includes: sequentially writing Nth?(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth?(N+K)th data to generate Nth?(N+K)th ECCs, respectively, where the Nth?(N+K)th ECCs are used to correct errors of the Nth?(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth?(N+K)th ECCs to generate the (N+K+1)th ECC.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 18, 2019
    Assignee: Silicon Motion Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 10324786
    Abstract: A method for managing data stored in a flash memory is provided, where the flash memory includes a plurality of blocks. The method includes: providing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks; detecting quality of a first block of the plurality of blocks to generate a detecting result, where the first block is the programmed block that has an earliest write time; and determining whether to move contents of the first block to a blank block, and to delete the contents of the first block according to the detecting result.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 18, 2019
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Li-Sheng Kan
  • Publication number: 20190173492
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Application
    Filed: January 17, 2019
    Publication date: June 6, 2019
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Publication number: 20190160298
    Abstract: A wireless electromagnetic thermotherapy apparatus applies a magnetic field on a needle for actuating heat generation thereby, and includes an excitation device and a detector device. The detector device includes a sensor unit that measures a temperature of the needle, a wireless charging unit that generates electrical energy in response to receipt of the magnetic field, a wireless transmitter that is powered by the electrical energy, and that transmits the measured temperature to the excitation device to enable the same to make a comparison between the measured temperature and a target temperature and to adjust an intensity of the magnetic field based on a result of the comparison.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 30, 2019
    Inventors: Tung-Chieh YANG, Yu-Jie LAN, Chien-Chang CHEN, Szu-Hua YANG, Yii-Der WU, Tsung-Chih YU
  • Publication number: 20190155531
    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
  • Patent number: 10289487
    Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 14, 2019
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 10276443
    Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chi Chen, Chih-Chung Chen, An-Chi Liu, Chih-Yueh Li, Pei-Ching Yeh, Tsung-Chieh Yang
  • Publication number: 20190121755
    Abstract: A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.
    Type: Application
    Filed: July 30, 2018
    Publication date: April 25, 2019
    Inventor: Tsung-Chieh Yang
  • Publication number: 20190122738
    Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventor: Tsung-Chieh Yang
  • Publication number: 20190121756
    Abstract: A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.
    Type: Application
    Filed: August 2, 2018
    Publication date: April 25, 2019
    Inventor: Tsung-Chieh Yang
  • Publication number: 20190086809
    Abstract: A method for cleaning masking material is provided. A sacrificial layer is patterned to form a masking material over a semiconductor structure. The method includes plasma striping a top surface of the masking material, and cleaning the masking material by a hot ammonia solution.
    Type: Application
    Filed: September 21, 2017
    Publication date: March 21, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Tsung-Chieh Yang, Chin-Che Hsu
  • Publication number: 20190089374
    Abstract: A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.
    Type: Application
    Filed: November 18, 2018
    Publication date: March 21, 2019
    Inventors: Tsung-Chieh Yang, Jian-Dong Du
  • Patent number: 10235075
    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: March 19, 2019
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
  • Patent number: 10236908
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 19, 2019
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Publication number: 20190073263
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 7, 2019
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Publication number: 20190074067
    Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 7, 2019
    Inventor: Tsung-Chieh Yang
  • Publication number: 20190050326
    Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.
    Type: Application
    Filed: October 15, 2018
    Publication date: February 14, 2019
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Publication number: 20190050287
    Abstract: The present invention provides a decoding method of a flash memory controller, wherein the decoding method includes the steps of: reading first data from a flash memory module; decoding the first data, and recording at least one specific address of the flash memory module according to decoding results of the first data, wherein said at least one specific address corresponds to a bit having high reliability errors (HRE) of the first data; reading second data from the flash memory module; and decoding the second data according to said at least one specific address.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 14, 2019
    Inventor: Tsung-Chieh Yang