Abstract: The present invention provides a method for accessing a flash memory module is disclosed, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of block, each block is implemented by a plurality of word lines, each word line corresponds to K pages, and each word line includes a plurality of memory cells supporting a plurality of states, and the method includes the steps of: receiving data from a host device; generating dummy data; and writing the data with the dummy data to a plurality of specific blocks, wherein for each of a portion of the word lines of the specific blocks, the dummy data is written into at least one of the K pages, and the data from the host device is written into the other page(s) of the K pages.

Abstract: A method and apparatus for performing access control of a memory device with aid of additional physical address information are provided. The method includes: during a garbage collection procedure, reading valid data from a source block and writing the valid data into a destination block; updating at least one logical-to-physical address mapping table; receiving a first read request from a host device, wherein the first read request indicates reading at a first logical address; in response to the first read request, reading the valid data of the destination block according to the second physical address associated with the first logical address; receiving a second read request from the host device, wherein the second read request indicates reading at the first logical address; and in response to the second read request, reading the valid data of the source block according to the first physical address associated with the first logical address.

Abstract: A method and apparatus for performing access control of a memory device with aid of additional physical address information are provided. The method includes: during a garbage collection procedure, reading valid data from a source block and writing the valid data into a destination block; updating at least one logical-to-physical address mapping table; receiving a first read request from a host device, wherein the first read request indicates reading at a first logical address; in response to the first read request, reading the valid data of the destination block according to the second physical address associated with the first logical address; receiving a second read request from the host device, wherein the second read request indicates reading at the first logical address; and in response to the second read request, reading the valid data of the source block according to the first physical address associated with the first logical address.

Abstract: A method and apparatus for performing access control of a memory device with aid of aggressor bit information are provided. The method includes: receiving a first host read command from a host device; sending a first read command to the NV memory in order to try reading first data from a first page; sending a second read command to the NV memory to obtain soft-decoding information and performing a first soft-decoding operation according to the soft-decoding information in order to try obtaining the first data from the first soft-decoding operation; reading multiple bits from at least one aggressor page to be the aggressor bit information; converting the soft-decoding information into adjusted soft-decoding information according to the aggressor bit information of the at least one aggressor page; and performing a second soft-decoding operation according to the adjusted soft-decoding information to obtain the first data from the second soft-decoding operation.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: The present invention proposes a method for managing a plurality of memory units in a flash memory module. The method includes: creating a programed timestamp corresponding to each first memory unit according to a data-written time of said each first memory unit; selecting a corresponding read-retry table for performing a read operation upon said each first memory unit according to the programed timestamp of said each first memory unit; and performing a first refresh operation according to program timestamps of first memory units that have been written with data.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: The present invention provides a method for access a flash memory module, wherein the method includes the steps of: sending a read command to the flash memory module to read a plurality of memory cells of at least one word line of the flash memory module by using a plurality of read voltages, wherein each memory cell is configured to store a plurality of bits, each memory cell has a plurality of states, the states are used to indicate different combinations of the plurality of bits; obtaining readout information from the flash memory module; analyzing the readout information to determine numbers of the states of the memory cells; determining if the memory cells are balance or unbalance according the numbers of the states of the memory cells to generate a determination result; and referring to the determination result to adjust voltage levels of the plurality of read voltages.

Abstract: The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.

Abstract: The present invention provides an electronic device, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is configured to access the flash memory module. In the operations of the electronic device, when the flash memory controller sends a read command to the flash memory module to ask for data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller.

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.

Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a plurality of sensing operations respectively corresponding to a plurality of sensing voltages to generate a first digital value and a second digital value of the Flash cell, the second digital value representing at least one candidate threshold voltage of the Flash cell; determining a threshold voltage of the Flash cell according to whether the at least one candidate threshold voltage is high or low; determining soft information of a bit stored in the Flash cell according to the threshold voltage of the Flash cell; and using the soft information to perform soft decoding.

Abstract: The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.

Abstract: The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.

Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a first sensing operation corresponding to a first sensing voltage to generate a first digital value of the Flash cell; according to a result of the first sensing operation, performing a plurality of second sensing operations to generate a second digital value of the Flash cell representing at least one candidate threshold voltage of the Flash cell; determining the threshold voltage of the memory Flash cell according to the at least one candidate threshold voltage; determining soft information of a bit stored in the Flash cell according to the threshold voltage of the Flash cell; and using the soft information to perform soft decoding.

Abstract: The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.