Abstract: The present invention proposes a method for managing a plurality of memory units in a flash memory module. The method includes: creating a programed timestamp corresponding to each first memory unit according to a data-written time of said each first memory unit; selecting a corresponding read-retry table for performing a read operation upon said each first memory unit according to the programed timestamp of said each first memory unit; and performing a first refresh operation according to program timestamps of first memory units that have been written with data.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract: A data storage system includes a processing circuit, a lookup table (LUT), and a decoding circuit. The processing circuit is arranged to receive a first logical block address (LBA) from a host. The LUT is arranged to store a storage address mapping to the first LBA. The decoding circuit is arranged to utilize the storage address to read storage data from a storing circuit, and decode a first data sector in the storage data according to an error checking and correcting code in the storage data, and the first data sector at least comprises a second LBA.

Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.

Abstract: A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.

Abstract: The present invention provides an encoder built-in self-test (BIST) circuit applied in a flash memory controller, wherein the encoder BIST circuit includes a control circuit and an encoder. In operations of the encoder BIST circuit, without accessing any flash memory, the control circuit generates input data to the encoder, and the encoder encodes the input data to generate a check code to the control circuit, wherein the check code is arranged to determine whether functions of the encoder fail or not.

Abstract: The present invention provides a decoding method of a flash memory controller, wherein the decoding method includes the steps of: reading first data from a flash memory module; decoding the first data, and recording at least one specific address of the flash memory module according to decoding results of the first data, wherein said at least one specific address corresponds to a bit having high reliability errors (HRE) of the first data; reading second data from the flash memory module; and decoding the second data according to said at least one specific address.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: A data storage system includes a processing circuit, a lookup table (LUT), and a decoding circuit. The processing circuit is arranged to receive a first logical block address (LBA) from a host. The LUT is arranged to store a storage address mapping to the first LBA. The decoding circuit is arranged to utilize the storage address to read storage data from a storing circuit, and decode a first data sector in the storage data according to an error checking and correcting code in the storage data, and the first data sector at least comprises a second LBA.

Abstract: A method for performing memory access includes: performing a first sensing operation corresponding to a first sensing voltage and performing at least a second sensing operation corresponding to a second sensing voltage to respectively generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value, the second digital value, and charge distribution statistics information of the Flash memory to obtain soft information of a bit stored in the Flash cell, wherein the soft information corresponds to a threshold voltage of the Flash cell; and using the soft information to perform soft decoding.

Abstract: A method for performing storage control in a storage server may include: regarding any memory device of a plurality of memory devices installed at the storage server, assigning a channel of multiple channels within the memory device for access control corresponding to a thread of a plurality of threads running on the storage server, wherein the storage server configures the plurality of memory devices to form a RAID of the storage server; and during storing a series of logical access units (LAUs) into the RAID, writing information into respective sets of pages of the plurality of memory devices as pages in a LAU of the series of LAUs according to a predetermined arrangement rule, to make the respective sets of pages be sequentially written into the plurality of memory devices respectively with aid of the assignment of the channel of the multiple channels to the thread. Associated apparatus are provided.

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, is disclosed to include at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method includes the steps of: sending a read command to the flash memory module to ask for data on at least one memory unit; receiving multi-bit information of a plurality of memory cells of the at least one memory unit from the flash memory module; and analyzing the multi-bit information of the plurality of memory cells to obtain a threshold voltage distribution of the plurality of memory cells for determining a decoding process.

Abstract: The present invention provides an electronic device, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is configured to access the flash memory module. In the operations of the electronic device, when the flash memory controller sends a read command to the flash memory module to ask for data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.

Abstract: A data storage system includes a processing circuit, a calculating circuit and an encoding circuit. The processing circuit receives a data byte from a host. The calculating circuit generates a cyclic redundancy check code according to an LBA, and combines the cyclic redundancy check code and the data byte into a data sector so that the data sector includes LBA-related information. The encoding circuit encodes the data sector to generate an error checking and correcting code, and combines the data sector and the error checking and correcting code into a storage data, so that the storage data includes the LBA-related information without including the LBA. Via the data sector and the storage data, the data storage system performs cyclic redundancy checking as well as error checking and correcting without storing the LBA for reducing 1-bit errors; and the LBA-related information does not include part or all of the LBA.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.