Abstract: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.

Abstract: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.

Abstract: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.

Abstract: In one embodiment, an method apparatus includes an optically clear adhesive (OCA) layer between a cover sheet and a substrate. The substrate has drive or sense electrodes of a touch sensor disposed on a first surface and a second surface of the substrate. The first surface is opposite the second surface and the drive or sense electrodes are made of a conductive mesh of conductive material including metal.

Abstract: An electrode pattern for a position sensing panel may have an array of mesh cells formed by sinusoidaly shaped conductive lines extending between vertices of the mesh cells.

Abstract: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.

Abstract: In one embodiment, a method performed by executing logic embodied by one or more computer-readable non-transitory storage media includes sending a first signal on a first line of a touch sensor. The first line includes a first plurality of electrodes. The method includes receiving a reflection of the first signal on the first line of the touch sensor. The method also includes determining coordinates of a touch on a device comprising the touch sensor in response to receiving the reflection of the first signal.

Abstract: An electrode pattern for a position sensing panel may have an array of mesh cells formed by sinusoidaly shaped conductive lines extending between vertices of the mesh cells.

Abstract: In one embodiment, a touch sensor includes one or more meshes of conductive material. Each of the meshes includes a plurality of conductive lines. A first one of the conductive lines has a first portion and a second portion. The first portion is wider than the second portion.

Abstract: In one embodiment, an method apparatus includes an optically clear adhesive (OCA) layer between a cover sheet and a substrate. The substrate has drive or sense electrodes of a touch sensor disposed on a first surface and a second surface of the substrate. The first surface is opposite the second surface and the drive or sense electrodes are made of a conductive mesh of conductive material including metal.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: Non-volatile semiconductor core memory performance is enhanced by reduced stress on core memory cells. Stress is reduced by selectable application of bias voltages to the sense line under control of the word line. The word line is connected to an inverting device in turn connected to a transistor effective for grounding the gate of a variable threshold programmable transistor in the memory cell. Power down of the word line is reflected in synchronous power-down of the sense line. Additionally, with power down, the sense amplifier for the particular core memory cell is disconnected from a master latch circuit, which in turn is connected to a slave latch circuit for applying the previous sense amplifier output to an input/output buffer, in order to secure the data sensed in core memory during read operation. The invention further permits reduced word line voltages during erase operation on the sense line and the variable threshold programmable transistor.

Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window.

Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window.

Abstract: A memory cell in an EPROM device which is totally sealed from ultraviolet light by a conductive cover without openings therein for leads to the cell's drain, source and gate. Electrical communication with the source is provided by direct contact with the conductive cover. Access to the drain and floating gate is provided by buried N+ implants, buried N+ layers or N-wells crossing underneath the sides of the cover. The memory cell has a single poly floating gate rather than a stacked floating gate/control gate combination. The buried N+ implant or N-well serves as the control gate and is capacitvely coupled to the floating gate via a thin oxide layer in a coupling area.

Abstract: A process of fabricating high performance EPROMs in which memory cell devices and high voltage circuit devices are formed in p-type tub regions of high threshold voltage. The tub regions are formed by implanting boron ions in photolithographically defined memory cell and high voltage device areas of a p-type wafer substrate, then subjecting the substrate to a high temperature drive-in. The N-channel isolation field is formed separately and has a lower threshold voltage than the tub regions. The isolation field is formed by implanting boron ions around all device areas, including low voltage device areas, using a nitride mask and a low implantation energy. The wafer is then subjected to an anneal step followed by a field oxidation step. The memory cell and other MOS devices are finally formed in the appropriate defined regions.

Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window.