Patents by Inventor Tsung-Fu Tsai

Tsung-Fu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128217
    Abstract: A semiconductor device includes a first semiconductor die and a second semiconductor die connected to the first semiconductor die. Each of the first semiconductor die and the second semiconductor die includes a substrate, a conductive bump formed on the substrate and a conductive contact formed on the conductive bump. The conductive contact has an outer lateral sidewall, there is an inner acute angle included between the outer lateral sidewall and the substrate is smaller than 85°, and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die.
    Type: Application
    Filed: January 20, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung CHEN, Chen Chiang YU, Wei-An TSAO, Tsung-Fu TSAI, Szu-Wei LU, Chung-Shi LIU
  • Publication number: 20240114703
    Abstract: A package structure and a formation method are provided. The method includes providing a semiconductor substrate and bonding a first chip structure on the semiconductor substrate through metal-to-metal bonding and dielectric-to-dielectric bonding. The method also includes bonding a second chip structure over the semiconductor substrate through solder-containing bonding structures. The method further includes forming a protective layer surrounding the second chip structure. A portion of the protective layer is between the semiconductor substrate and a bottom of the second chip structure.
    Type: Application
    Filed: February 2, 2023
    Publication date: April 4, 2024
    Inventors: Tsung-Fu TSAI, Szu-Wei LU, Shih-Peng TAI, Chen-Hua YU
  • Patent number: 11948896
    Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
  • Publication number: 20240105629
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Szu-Wei Lu, Tsung-Fu Tsai
  • Patent number: 11923259
    Abstract: A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Tsung-Fu Tsai
  • Publication number: 20240071982
    Abstract: In an embodiment, a device bonding apparatus is provided. The device bonding apparatus includes a first process station configured to receive a wafer; a first bond head configured to carry a die to the wafer, wherein the first bonding head includes a first rigid body and a vacuum channel in the first rigid body for providing an attaching force for carrying the die to the wafer; and a second bond head configured to press the die against the wafer, the second bond head including a second rigid body and an elastic head disposed over the second rigid body for pressing the die, the elastic head having a center portion and an edge portion surrounding the center portion, the center portion of the elastic head having a first thickness, the edge portion of the elastic head having a second thickness, the second thickness being greater than the second thickness.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20240063204
    Abstract: Integrated circuit package structures and methods of forming integrated circuit package structures are discussed. An integrated circuit package structure, in accordance with some embodiments, includes an integrated circuit package substrate with a heterogeneous bonding scheme that includes conductive pillars for bonding semiconductor devices to as well as a region including conductive connectors embedded in a dielectric for bonding additional semiconductor devices.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu, Chung-Shi Liu
  • Publication number: 20240063043
    Abstract: A method for forming a semiconductor device is provided. The method includes providing a wafer with multiple semiconductor dies on the adhesive film held by the frame element. The method also includes lifting a semiconductor die up from the wafer using an ejector element. The method includes picking up the semiconductor die with a collector element. The method further includes flip-chipping the semiconductor die with the collector element, and picking up the semiconductor die from the collector element using a bond-head element. In addition, the method includes measuring the warpage of the semiconductor die on the bond-head element using a sensor, then bonding the semiconductor die to a carrier using the bond-head element.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: Yi-Jung CHEN, Tsung-Fu TSAI, Szu-Wei LU, Chung-Shi LIU
  • Publication number: 20240055410
    Abstract: A package structure is provided. The package structure includes a substrate and a semiconductor chip over the substrate. The package structure also includes a protective frame laterally surrounding the semiconductor chip. The package structure further includes an underfill element between the semiconductor chip and the protective frame. A portion of the underfill element is directly below the protective frame.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 15, 2024
    Inventors: Chen-Hsuan TSAI, Tsung-Fu TSAI, Shih-Ting LIN, Szu-Wei LU
  • Publication number: 20240021491
    Abstract: A semiconductor device includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die includes a conductive paste on a first surface of the first integrated circuit die, wherein the conductive paste is in direct contact with the first surface of the first integrated circuit die. The second integrated circuit die is disposed aside the first integrated circuit die, wherein a surface of the conductive paste is substantially coplanar with a surface of the second integrated circuit die.
    Type: Application
    Filed: July 17, 2022
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Tsung-Fu Tsai, Hung-Chih Chen, Chin-Chuan Chang
  • Publication number: 20240021442
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Application
    Filed: August 1, 2023
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Publication number: 20240014162
    Abstract: A package structure includes a semiconductor die, a first insulating encapsulant, a plurality of first conductive features, an interconnect structure and bump structures. The semiconductor die includes a plurality of conductive pillars made of a first material. The first insulating encapsulant is encapsulating the semiconductor die. The first conductive features are disposed on the semiconductor die and electrically connected to the conductive pillars. The first conductive features include at least a second material different from the first material. The interconnect structure is disposed on the first conductive features, wherein the interconnect structure includes a plurality of connection structures made of the second material. The bump structures are electrically connecting the first conductive features to the connection structures, wherein the bump structures include a third material different from the first material and the second material.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20240006268
    Abstract: A package structure includes a circuit substrate, a semiconductor device, a plurality of cooling pins, a cooler lid, an anti-fouling coating and a top lid. The semiconductor device is disposed on and electrically connected to the circuit substrate. The cooling pins are disposed on the semiconductor device. The cooler lid is attached to the cooling pins, wherein the cooler lid includes an inlet opening and an outlet opening exposing portions of the cooling pins. The anti-fouling coating is coated on the cooling pins and on an inner surface of the cooler lid. The top lid is attached to an outer surface of the cooler lid.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Chiang Yu, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20230417993
    Abstract: A package includes a laser diode includes a bonding layer; a first dielectric layer over the laser diode, wherein the first dielectric layer is directly bonded to the bonding layer of the laser diode; a first silicon nitride waveguide in the first dielectric layer, wherein the first silicon nitride waveguide extends over the laser diode; a second dielectric layer over the first silicon nitride waveguide; a silicon waveguide in the second dielectric layer; an interconnect structure over the silicon waveguide; and conductive features extending through the first dielectric layer and the second dielectric layer to electrically contact the interconnect structure.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Tsung-Fu Tsai, Hsing-Kuo Hsia, Szu-Wei Lu, Chen-Hua Yu
  • Patent number: 11854984
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Szu-Wei Lu, Tsung-Fu Tsai
  • Patent number: 11855060
    Abstract: A package structure includes a circuit substrate, a semiconductor package, a lid structure and a plurality of first spacer structures. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures is surrounding the semiconductor package, wherein the first spacer structures are sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Chin-Fu Kao, Pu Wang, Szu-Wei Lu
  • Publication number: 20230402345
    Abstract: A semiconductor package including a cooling system and a method of forming are provided. The semiconductor package may include an interposer, one or more package components bonded to the interposer, an encapsulant on the interposer, and a cooling system over the one or more package components. The cooling system may include one or more metal layers on top surfaces of the one or more package components, first metal pins on the one or more metal layers, second metal pins, wherein each of the second metal pins may be bonded to a corresponding one of the first metal pins by solder, and a first lid over the second metal pins, wherein the first lid may include openings.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 14, 2023
    Inventors: Chen Chiang Yu, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20230402346
    Abstract: A device includes a package substrate, an interposer having a first side bonded to the package substrate, a first die bonded to a second side of the interposer, the second side being opposite the first side, a ring on the package substrate, where the ring surrounds the first die and the interposer, a molding compound disposed between the ring and the first die, where the molding compound is in physical contact with the ring, and a plurality of thermal-conductive layers over and in physical contact with the molding compound and the first die, where the molding compound is disposed between the plurality of thermal-conductive layers and the ring.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: Szu-Wei Lu, Tsung-Fu Tsai, Chi-Hsiang Chen
  • Publication number: 20230369370
    Abstract: A package structure includes an optical die, an optical die, a supporting structure, and a lens structure. The optical die includes a photonic region. The optical die is disposed on and electrically coupled to the optical die. The supporting structure is disposed on the optical die, where the electric die is disposed between the supporting structure and the optical die. The lens structure is disposed on the supporting structure and optically coupled to the photonic region of the optical die, where the supporting structure is disposed between the lens structure and the electric die.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu, Wei-An Tsao, Che-Yuan Yang, Chien-Ting Chen, Chih-Chieh Hung
  • Patent number: 11817425
    Abstract: A package structure is provided. The package structure includes a substrate and a stack of semiconductor dies over the substrate. The package structure also includes an underfill element covering sidewalls of the semiconductor dies. The package structure further includes a protective film attached to the substrate and laterally surrounding the underfill element and the semiconductor dies. The underfill element separates the protective film from the semiconductor dies.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hsuan Tsai, Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu