Patents by Inventor Tsung-Fu Tsai
Tsung-Fu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10985140Abstract: A structure and a formation method of a package structure are provided. The method includes disposing a semiconductor die structure over a substrate. The method also includes disposing a protective film over the substrate. The protective film has an opening exposing the semiconductor die structure, and sidewalls of the opening surround the semiconductor die structure. The method further includes dispensing an underfill material into the opening to surround the semiconductor die structure.Type: GrantFiled: April 15, 2019Date of Patent: April 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hsuan Tsai, Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu
-
Publication number: 20210098386Abstract: An electronic device and a manufacturing method thereof are provided. The method includes at least the following steps. An insulating encapsulant is formed to encapsulate a multi-layered structure and a semiconductor die, where the multi-layered structure includes a first conductor, a diffusion barrier layer on the first conductor, and a metallic layer on the diffusion barrier layer, and the insulating encapsulant at least exposes a portion of the semiconductor die and a portion of the first conductor. A redistribution structure is formed over the insulating encapsulant, the semiconductor die, and the first conductor. The metallic layer is removed to form a recess in the insulating encapsulant. A second conductor is formed in the recess over the diffusion barrier layer, where the first conductor, the diffusion barrier layer, and the second conductor form a conductive structure that is electrically coupled to the semiconductor die through the redistribution structure.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Hou-Ju Huang, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai
-
Publication number: 20210091005Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.Type: ApplicationFiled: March 2, 2020Publication date: March 25, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Szu-Wei Lu, Tsung-Fu Tsai
-
Publication number: 20210066211Abstract: A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.Type: ApplicationFiled: May 4, 2020Publication date: March 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, Li-Chung Kuo, Szu-Wei Lu, Ying-Ching Shih
-
Patent number: 10923438Abstract: A package structure and method for forming the same are provided. The method includes forming a through substrate via structure in a substrate, and forming a first trench in the substrate. The method includes stacking a first stacked die package structure over the substrate using a plurality of first bonding structures. The first bonding structures are between the substrate and the first stacked die package structure, and a there is plurality of cavities between two adjacent first bonding structures. The method also includes forming an underfill layer over the first stacked die package structure and in the cavities, and the underfill layer is formed in a portion of the first trench. The method further includes forming a package layer over the underfill layer.Type: GrantFiled: April 26, 2019Date of Patent: February 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
-
Patent number: 10867919Abstract: An electronic device and the manufacturing method thereof are provided. The electronic device includes a semiconductor die, a conductive structure electrically coupled to the semiconductor die, an insulating encapsulant encapsulating the semiconductor die and the conductive structure, and a redistribution structure disposed on the insulating encapsulant and the semiconductor die. The conductive structure includes a first conductor, a second conductor, and a diffusion barrier layer between the first conductor and the second conductor. The redistribution structure is electrically connected to the semiconductor die and the first conductor of the conductive structure.Type: GrantFiled: September 19, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Hou-Ju Huang, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai
-
Publication number: 20200365557Abstract: A semiconductor package includes a first integrated circuit structure, a second integrated circuit structure, a plurality of conductive bumps, an encapsulating material, and a redistribution structure. The first integrated circuit structure includes an active surface having a plurality of contact pads, a back surface opposite to the active surface, and a plurality of through vias extending through the first integrated circuit structure and connecting the active surface and the back surface. The second integrated circuit structure is disposed on the back surface of the first integrated circuit structure. The conductive bumps are disposed between the first integrated circuit structure and the second integrated circuit structure, and electrically connecting the plurality of through vias and the second integrated circuit structure. The encapsulating material at least encapsulates the second integrated circuit structure.Type: ApplicationFiled: May 16, 2019Publication date: November 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Ying-Ching Shih
-
Publication number: 20200343198Abstract: A package structure and method for forming the same are provided. The method includes forming a through substrate via structure in a substrate, and forming a first trench in the substrate. The method includes stacking a first stacked die package structure over the substrate using a plurality of first bonding structures. The first bonding structures are between the substrate and the first stacked die package structure, and a there is plurality of cavities between two adjacent first bonding structures. The method also includes forming an underfill layer over the first stacked die package structure and in the cavities, and the underfill layer is formed in a portion of the first trench. The method further includes forming a package layer over the underfill layer.Type: ApplicationFiled: April 26, 2019Publication date: October 29, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Fu TSAI, Kung-Chen YEH, I-Ting HUANG, Shih-Ting LIN, Szu-Wei LU
-
Publication number: 20200328185Abstract: A structure and a formation method of a package structure are provided. The method includes disposing a semiconductor die structure over a substrate. The method also includes disposing a protective film over the substrate. The protective film has an opening exposing the semiconductor die structure, and sidewalls of the opening surround the semiconductor die structure. The method further includes dispensing an underfill material into the opening to surround the semiconductor die structure.Type: ApplicationFiled: April 15, 2019Publication date: October 15, 2020Inventors: Chen-Hsuan TSAI, Tsung-Fu TSAI, Shih-Ting LIN, Szu-Wei LU
-
Patent number: 10770366Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.Type: GrantFiled: November 25, 2019Date of Patent: September 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
-
Publication number: 20200091027Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
-
Publication number: 20200091077Abstract: An electronic device and the manufacturing method thereof are provided. The electronic device includes a semiconductor die, a conductive structure electrically coupled to the semiconductor die, an insulating encapsulant encapsulating the semiconductor die and the conductive structure, and a redistribution structure disposed on the insulating encapsulant and the semiconductor die. The conductive structure includes a first conductor, a second conductor, and a diffusion barrier layer between the first conductor and the second conductor. The redistribution structure is electrically connected to the semiconductor die and the first conductor of the conductive structure.Type: ApplicationFiled: September 19, 2018Publication date: March 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Fu Tsai, Hou-Ju Huang, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai
-
Publication number: 20200058519Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate, a die stacking unit, a number of dummy micro bumps, and an underfill material. The die stacking unit, which is mounted on the base substrate, includes a first die, a second die, and a number of first conductive joints. The first die and the second die are stacked on each other, and the first conductive joints are disposed between and connected to the first die and the second die. The dummy micro bumps, which are disposed between the first conductive joints, are connected to the first die but not to the second die. The underfill material is filled into a number of gaps between the base substrate, the first die, the second die, the first conductive joints, and the dummy micro bumps.Type: ApplicationFiled: November 1, 2018Publication date: February 20, 2020Inventors: Tsung-Fu TSAI, Chen-Hsuan TSAI, Chung-Chieh TING, Shih-Ting LIN, Szu-Wei LU
-
Patent number: 10510635Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.Type: GrantFiled: June 29, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
-
Patent number: 10453818Abstract: A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.Type: GrantFiled: January 26, 2018Date of Patent: October 22, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Chia-Wei Tu, Yian-Liang Kuo, Ru-Ying Huang
-
Patent number: 10269762Abstract: A rework process includes attaching a first bond head to a first semiconductor package. The contact pads of the first semiconductor package are bonded to contact pads of a second semiconductor package by solder joints. The rework process further includes performing a first local heating process to melt the solder joints, removing the first semiconductor package using the first bond head, and removing at least a portion of solder from the contact pads of the second semiconductor package.Type: GrantFiled: October 29, 2015Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Ting Lin, Justin Huang, Tsung-Fu Tsai, Jing-Cheng Lin, Chen-Hua Yu
-
Patent number: 10269750Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.Type: GrantFiled: May 22, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Wei Tu, Yian-Liang Kuo, Tsung-Fu Tsai, Ru-Ying Huang, Ming-Song Sheu, Hsien-Wei Chen
-
Publication number: 20180366439Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jing-Cheng Lin, Tsung-Fu Tsai, Chen-Hua Yu, Po-Hao Tsai, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai, Chen-Hsuan Tsai
-
Patent number: 10157888Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.Type: GrantFiled: June 20, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jing-Cheng Lin, Tsung-Fu Tsai, Chen-Hua Yu, Po-Hao Tsai, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai, Chen-Hsuan Tsai
-
Publication number: 20180308778Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo