Abstract: A reflective liquid crystal display panel capable of performing data programming and/or data erasing via a polarized light is provided. The reflective liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, a transflective film, a retarder and a polarizer. The second substrate is disposed over the first substrate. The liquid crystal layer is located between the first substrate and the second substrate and an optical aligned material is doped in the liquid crystal layer. The transflective film is disposed below the first substrate, and the transflective film allows the polarized light to pass through, so that the orientation of the optical aligned material doped liquid crystal layer can be controlled by the polarized light. The transflective film reflects external light source. The retarder is disposed between the transflective film and the first substrate. The polarizer is disposed on the second substrate.

Abstract: A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.

Abstract: A method of fabricating a thin film transistor is provided. A gate is formed on a substrate. A gate insulator is formed on the substrate to cover the gate. A source/drain layer is formed on the gate insulator, and a portion of the gate insulator above the gate is exposed by the source/drain layer. An isolated layer is formed on the source/drain layer and has an opening to expose a portion of the gate insulator and a portion of the source/drain layer above the gate. A channel layer is formed in the opening of the isolated layer to be electrically connected to the source/drain layer, and the channel layer is exposed by the opening.

Abstract: A fabricating method of organic electronic device is provided. The method comprises: providing a flexible substrate; fabricating a plurality of organic elements on the flexible substrate; fabricating a patterned spacing layer on the flexible substrate; and arranging a cover substrate on the patterned spacing layer, and sealing the edges of the flexible substrate and the cover substrate with a sealant, wherein the patterned spacing layer is used to maintain a space between the flexible substrate and the cover substrate.

Abstract: An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-pattern regions for optimizing a subsequent trench process and simplifying process steps.

Abstract: The present invention provides a reflective liquid crystal display assembly, which includes a first substrate, a second substrate and a liquid crystal layer sealed between them. The present invention designs a specific surface structure of at least one of the first and second substrates relative to the liquid crystal layer so that the helical axes of the cholesteric liquid crystal molecules can incline in different directions as desired in the liquid crystal layer. The reflective spectrum can be broadened and the viewing angle is widened.

Abstract: Calibration of a phase locked loop and applications thereof within a radio frequency integrated circuit begins by determining an intersection of an up current and down current produced by a charge pump within the phase locked loop. The RFIC then determines a reference voltage corresponding to the intersection, which varies from an ideal voltage of VDD/2 based on process variations. The RFIC then offsets a control voltage to the voltage control oscillator (VCO) of the phase locked loop based on the reference voltage. Accordingly, by determining the offset of the actual intersection from the ideal intersection, the control voltage to the VCO may be adjusted thereby calibrating the phase locked loop for more linear performance.

Abstract: An analog open-loop voltage controlled oscillator (VCO) calibration circuit and method for selecting the frequency of the VCO for a phase locked loop (PLL). A frequency divider module produces a 50% duty cycle divided local oscillation and a 50% duty cycle divided reference signal, wherein the divided signals are substantially equal. A period-to-voltage conversion module converts the divided local oscillation signal and the divided reference signal to voltages proportional to the divided signals. A comparator module produces a frequency adjustment signal based on a comparison of the proportional voltages and couples the frequency adjustment signal to a logic module which produces a frequency compensation signal based on the frequency adjustment signal. The frequency compensation signal functions to adjust the configuration of switched capacitors in a capacitor bank, coupled to the VCO tuned circuit, until the divided local oscillation signal is substantially equal to the divided reference signal.

Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

Abstract: An output method for improving video image quality is provided. First, a frame data of a first frame is received, wherein the first frame may coincide with a first type or a second type. Thereafter, the first frame is subjected to a signal process step to output a processed first frame with a first standard, wherein the processed first frame comprises a first signal to noise (S/N) ratio. Next, a frame data of a second frame with a second standard is received, wherein the second frame coincides with a third type. Thereafter, a first decompression process of frame data is performed on the second frame to output a processed second frame with the first standard, wherein the processed second frame comprises a second S/N ratio. In addition, a difference between the first S/N ratio and the second S/N ratio is smaller than a predetermined minimum tolerance.

Abstract: A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.

Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output.

Abstract: A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.

Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

Abstract: A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably coupled to produce a divider value based on a control signal. The logic circuit is operably coupled to produce the control signal based on divider select signals. Each of the plurality of flip-flops includes a first differential latch module, a second differential latch module. The first differential latch module is operably coupled to produce a differential latched signal based on a differential flip-flop input signal. The second differential latch module is operably coupled to produce a differential flip-flop output based on the differential latched signal. Each of the first and second differential latch modules includes a sample transistor section, a hold transistor section, a first gating circuit, and a second gating circuit.

Abstract: A radio transceiver includes a charge pump formed within a local oscillator that adjusts a voltage input to a voltage-controlled oscillator in a manner that flattens a response curve for small changes in voltage due to a variety of effects including channel length modulation. Thus, a local oscillation tends to provide a greater degree of stability. More specifically, the charge pump of the transceiver includes a pair of feedback circuits that source an additional amount of current into a filter to slightly increase a voltage input to the voltage-controlled oscillator in response to small upward changes in output voltage levels (input with respect to the voltage-controlled oscillator). Similarly, when the output voltage level drops slightly, a second feedback circuit causes a small amount of current to be sinked from the output node thereby slightly decreasing the input voltage to the voltage-controlled oscillator.

Abstract: Embodiments of an optical compensator for a liquid crystal display is disclosed. One embodiment of the optical compensator includes an A-plate and a C-plate wherein: the retardation of the A-plate satisfies the following formula: 0.644<R0(450)/R0(550)<1 the retardation of the C-plate satisfies the following formula: 1<Rth(450)/Rth(550)<1.35 where R0(450) and R0(550) represent the retardation of the A-plate at wavelengths of 450 nm and 550 nm, respectively, and Rth(450) and Rth(550) are the values calculated by Rth=[[nx+ny]/2?nz]×d (where nx, ny and nz represent the three-dimensional refractive indexes of the C-plate as the refractive indexes in the direction of the x-axis, y-axis and z-axis, respectively, and d represents the thickness of the C-plate) for the C-plate at a wavelength of 450 nm and 550 nm, respectively. Other embodiments are also included.

Abstract: A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably coupled to produce a divider value based on a control signal. The logic circuit is operably coupled to produce the control signal based on divider select signals. Each of the plurality of flip-flops includes a first differential latch module, a second differential latch module. The first differential latch module is operably coupled to produce a differential latched signal based on a differential flip-flop input signal. The second differential latch module is operably coupled to produce a differential flip-flop output based on the differential latched signal. Each of the first and second differential latch modules includes a sample transistor section, a hold transistor section, a first gating circuit, and a second gating circuit.