Abstract: Systems and method directed to digital pattern generator (DPG) having a mirror array in an e-beam lithography system are discussed. The mirror array includes a first bank of mirrors and a second bank of mirrors with a combination logic structure interposing the first and second banks of mirrors. An output data line extends from the first bank of mirrors to the combinational logic structure. An input data line that carries data associated with the second bank of mirrors is also provided to the combinational logic structure. An output data line extends from the combinational logic structure to second data bank.

Abstract: The present disclosure provides a method for operating a dynamic pattern generator (DPG) having a mirror array. The method comprises receiving a clock signal, determining a time delay based on the period of the clock signal, determining a first clock signal for toggling a first group of mirror cells in the mirror array, determining a second clock signal, lagging behind the first clock signal by the time delay, for toggling a second group of mirror cells in the mirror array, toggling the first group of mirror cells in the mirror array in response to the first clock signal, and toggling the second group of the mirror cells in the mirror array in response to the second clock signal.

Abstract: A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data.

Abstract: One or more circuits are provided wherein leakage current is mitigated. A circuit comprises a pad, a first transistor, a second transistor, a power leakage component and a data leakage component. The first transistor and the second transistor are respectively configured to control a voltage level at the pad. The first transistor is connected to the pad and to a first voltage source. The second transistor is connected to the pad and to a third voltage source. The power leakage component is connected between the first transistor and the pad. The data leakage component is connected between the second transistor and the pad. The power leakage component is configured to mitigate leakage current from the first transistor to the pad. The data leakage component is configured to mitigate leakage current from the pad to the second transistor.

Abstract: A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data.

Abstract: A circuit includes a supply voltage node having a supply voltage value and a node having a node voltage, the node voltage having a node voltage value higher than the supply voltage value. A current generating circuit is coupled between the supply voltage node and the node and is configured to generate a current, and a tracking circuit electrically coupled to the node is configured to selectively supply the current to the node based on the node voltage.

Abstract: The present disclosure provides a method for operating a dynamic pattern generator (DPG) having a mirror array. The method comprises receiving a clock signal, determining a time delay based on the period of the clock signal, determining a first clock signal for toggling a first group of mirror cells in the mirror array, determining a second clock signal, lagging behind the first clock signal by the time delay, for toggling a second group of mirror cells in the mirror array, toggling the first group of mirror cells in the mirror array in response to the first clock signal, and toggling the second group of the mirror cells in the mirror array in response to the second clock signal.

Abstract: A method of lithography including providing a first mirror array and a second mirror array of a digital pattern generator (DPG); the second mirror array is offset from the first mirror array in a first direction. A first data piece and a second data piece associated with an IC device, are received by the DPG. The first and second data piece each defines a state of a pixel of the DPG. The first data piece is provided to a first pixel of the DPG. The second data piece is also provided to the first pixel of the DPG. A first point on a photosensitive layer on a target substrate is exposed. The first point is defined by the first data piece and the second data piece. The target substrate moved in a second direction, perpendicular to the first direction to expose a second point.

Abstract: A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor.

Abstract: A method for operating a dynamic pattern generator (DPG) has a mirror array, where an operating clock of the DPG is received and converted to a toggling rate dependent on the operating clock. The toggling rate is compared with a threshold. If the toggling rate is greater than the threshold, the method partitions the mirror array into a plurality of groups. In response to the groups, the method determines a delay value based on the operating clock. The method further generates a delayed clock with the delay with respect to the first clock to the groups of the mirror array.

Abstract: A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage.

Abstract: A method of lithography including providing a first mirror array and a second mirror array of a digital pattern generator (DPG); the second mirror array is offset from the first mirror array in a first direction. A first data piece and a second data piece associated with an IC device, are received by the DPG. The first and second data piece each defines a state of a pixel of the DPG. The first data piece is provided to a first pixel of the DPG. The second data piece is also provided to the first pixel of the DPG. A first point on a photosensitive layer on a target substrate is exposed. The first point is defined by the first data piece and the second data piece. The target substrate moved in a second direction, perpendicular to the first direction to expose a second point.

Abstract: Systems and method directed to digital pattern generator (DPG) having a mirror array in an e-beam lithography system are discussed. The mirror array includes a first bank of mirrors and a second bank of mirrors with a combination logic structure interposing the first and second banks of mirrors. An output data line extends from the first bank of mirrors to the combinational logic structure. An input data line that carries data associated with the second bank of mirrors is also provided to the combinational logic structure. An output data line extends from the combinational logic structure to second data bank.

Abstract: One or more circuits are provided wherein leakage current is mitigated. A circuit comprises a pad, a first transistor, a second transistor, a power leakage component and a data leakage component. The first transistor and the second transistor are respectively configured to control a voltage level at the pad. The first transistor is connected to the pad and to a first voltage source. The second transistor is connected to the pad and to a third voltage source. The power leakage component is connected between the first transistor and the pad. The data leakage component is connected between the second transistor and the pad. The power leakage component is configured to mitigate leakage current from the first transistor to the pad. The data leakage component is configured to mitigate leakage current from the pad to the second transistor.

Abstract: A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (FSM) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from the second-order phase code. A multiplexing is performed to the plurality of candidate total phase codes to output one of the plurality of candidate total phase codes as a total phase code. The multiplexing is controlled by the first-order phase code. A brake machine may be implemented to prevent over-compensation of phases.

Abstract: A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor.

Abstract: In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

Abstract: A voltage swing decomposition circuit includes first and second clamp circuits and a protection circuit. The first clamp circuit is configured to clamp an output node of the first clamp circuit at a first voltage level when an input node of the voltage swing decomposition circuit has a voltage higher than the first voltage level. The second clamp circuit is configured to clamp an output node of the second clamp circuit at a second voltage level, higher than the first level, when the voltage of the input node is lower than the second voltage level. The protection circuit is coupled to the output nodes of the first and second clamp circuits, and is configured to selectively set an output node of the protection circuit to the first or second voltage level. The first and second clamp circuits are coupled together by the output node of the protection circuit.

Abstract: A D flip-flop includes a first switch, a level shifter, and a second switch therein. The first switch includes a first input and a first output. The level shifter includes a second input coupled to the first input, and a second output. The second switch includes a third input coupled to the second output, and a third output. The first input and the third output form an input and an output of the D flip-flop.

Abstract: A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (FSM) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from the second-order phase code. A multiplexing is performed to the plurality of candidate total phase codes to output one of the plurality of candidate total phase codes as a total phase code. The multiplexing is controlled by the first-order phase code. A brake machine may be implemented to prevent over-compensation of phases.