Abstract: The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.

Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.

Abstract: Some embodiments of the present disclosure provide a semiconductor structure including a substrate and an epitaxy region partially disposed in the substrate. The epitaxy region includes a substance with a lattice constant that is larger than a lattice constant of the substrate. The concentration profile of a substance in the epitaxy region is monotonically increasing from a bottom portion of the epitaxy region to a of the epitaxy region. A first layer of the epitaxy region has a height to width ratio of about 2. The first layer is a layer positioned closest to the substrate, and the first layer has an average concentration of the substance from about 20 to about 32 percent. A second layer disposed over the first layer. The second layer has a bottom portion with a concentration of the substance from about 27 percent to about 37 percent.

Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate and a regrowth region. The substrate is made of a first material with a first lattice constant, and the regrowth region is made of the first material and a second material, having a lattice constant different from the first lattice constant. The regrowth region is partially positioned in the substrate. The regrowth region has a “tip depth” measured vertically from a surface of the substrate to a widest vertex of the regrowth region, and the tip depth being less than 10 nm. The regrowth region further includes a top layer substantially made of the first material, and the top layer has substantially the first lattice constant.

Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.

Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.

Abstract: A semiconductor device includes a nanowire structure and a stressor. The nanowire structure includes a first channel section and a second channel section. The stressor subjects the first channel section to a first strain level and the second channel section to a second strain level greater than the first strain level. The difference between the second strain level and the first strain level is less than the second strain level.

Abstract: A semiconductor device and method of forming the same are described. A semiconductor device includes an active area adjacent a channel in a semiconductor composite. The active area includes a first active area layer having a first dopant concentration, a second active area layer having a second dopant concentration over the first active area layer, and a third active area layer having a third dopant concentration, over the second active area. The third dopant concentration is greater than the second dopant concentration, and the second dopant concentration is greater than the first dopant concentration. The channel includes a second channel layer comprising carbon over a first channel layer and a third channel layer over the second channel layer. The active area configuration improves drive current and reduces contact resistance, and the channel configuration increases short channel control, as compared to a semiconductor device without the active area and channel configuration.

Abstract: A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract: A semiconductor device is provided having a channel formed from a nanowire with multi-level band gap energy. The semiconductor device comprises a nanowire structure formed between source and drain regions. The nanowire structure has a first band gap energy section joined with a second band gap energy section. The first band gap energy section is coupled to the source region and has a band gap energy level greater than the band gap energy level of the second band gap energy section. The second band gap energy section is coupled to the drain region. The first band gap energy section comprises a first material and the second band gap energy section comprises a second material wherein the first material is different from the second material. The semiconductor device further comprises a gate region around the junction between the first band gap energy section and the second band gap energy section.

Abstract: A semiconductor device with multi-level work function and multi-valued channel doping is provided. The semiconductor device comprises a nanowire structure and a gate region. The nanowire structure is formed as a channel between a source region and a drain region. The nanowire structure has a first doped channel section joined with a second doped channel section. The first doped channel section is coupled to the source region and has a doping concentration greater than the doping concentration of the second doped channel section. The second doped channel section is coupled to the drain region. The gate region is formed around the junction at which the first doped section and the second doped section are joined. The gate region has a first work function gate section joined with a second work function gate section. The first work function gate section is located adjacent to the source region and has a work function greater than the work function of the second work function gate section.

Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.

Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.

Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel.

Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.

Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel.

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract: A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0° and less than 90°.

Abstract: The present disclosure relates to method of forming a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated device. The method forms a first dislocation stress memorization (DSM) region and a second DSM region having stressed lattices within a substrate. The substrate is selectively etched to form a source cavity and a drain cavity extending from an upper surface of the substrate to positions contacting the first DSM region and the second DSM region. An epitaxial source is formed within the source cavity and an epitaxial drain region is formed within the drain cavity. A gate structure is formed over the substrate at a location laterally between the epitaxial source region and the epitaxial drain region.