Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated method of formation. The transistor device has an epitaxial stack disposed over a semiconductor substrate, and a gate structure disposed over the epitaxial stack. A channel region extends below the gate structure between epitaxial source and drain regions located on opposing sides of the gate structure. First and second dislocation stress memorization (DSM) regions have a stressed lattice that generates stress within the channel region. The first and second DSM regions respectively extend from below the epitaxial source region to a first location within the epitaxial source region from below the epitaxial drain region to a second location within the epitaxial drain region. Using the first and second DSM regions to stress the channel region, improves device performance.

Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.

Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel.

Abstract: A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.

Abstract: A method for improving analog gain in long channel devices associated with a semiconductor workpiece is provided. A gate oxide layer is formed on the semiconductor workpiece, and a plurality of gate structures are formed over the gate oxide layer, wherein a first pair of the plurality of gate structures define a short channel device region and a second pair of the plurality of gate structures define a long channel device region. A first ion implantation with a first dopant is performed at a first angle, wherein the first dopant is one of an n-type dopant and a p-type dopant. A second ion implantation with a second dopant is performed at a second angle, wherein the second angle is greater than the first angle. The second dopant is one or an n-type dopant and a p-type dopant that is opposite of the first dopant, and a height of the plurality of gate structures and the second angle generally prevents the second ion implantation from implanting ions into the short channel device region.

Abstract: A semiconductor device with multi-level work function and multi-valued channel doping is provided. The semiconductor device comprises a nanowire structure and a gate region. The nanowire structure is formed as a channel between a source region and a drain region. The nanowire structure has a first doped channel section joined with a second doped channel section. The first doped channel section is coupled to the source region and has a doping concentration greater than the doping concentration of the second doped channel section. The second doped channel section is coupled to the drain region. The gate region is formed around the junction at which the first doped section and the second doped section are joined. The gate region has a first work function gate section joined with a second work function gate section. The first work function gate section is located adjacent to the source region and has a work function greater than the work function of the second work function gate section.

Abstract: A semiconductor device is provided having a channel formed from a nanowire with multi-level band gap energy. The semiconductor device comprises a nanowire structure formed between source and drain regions. The nanowire structure has a first band gap energy section joined with a second band gap energy section. The first band gap energy section is coupled to the source region and has a band gap energy level greater than the band gap energy level of the second band gap energy section. The second band gap energy section is coupled to the drain region. The first band gap energy section comprises a first material and the second band gap energy section comprises a second material wherein the first material is different from the second material. The semiconductor device further comprises a gate region around the junction between the first band gap energy section and the second band gap energy section.

Abstract: A semiconductor device having a channel formed from a nanowire with a multi-dimensional diameter is provided. The semiconductor device comprises a drain region formed on a semiconductor substrate. The semiconductor device further comprises a nanowire structure formed between a source region and the drain region. The nanowire structure has a first diameter section joined with a second diameter section. The first diameter section is coupled to the drain region and has a diameter greater than the diameter of the second diameter section. The second diameter section is coupled to the source region. The semiconductor device further comprises a gate region formed around the junction at which the first diameter section and the second diameter section are joined.

Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.

Abstract: Some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate DIBL, both long-channel and short-channel transistors on a substrate are subjected to a halo implant. While the halo implant improves short-channel transistor performance, it degrades long-channel transistor performance. Therefore, a counter-halo implant is performed on the long-channel transistors only to restore their performance. To achieve this, the counter-halo implant is performed at an angle that introduces dopant impurities near the source/drain regions of the long-channel transistors to counteract the effects of the halo implant, while the counter-halo implant is simultaneously shadowed from reaching the channel of the short-channel transistors.

Abstract: The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.

Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel.

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.

Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.

Abstract: A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0° and less than 90°.