Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.

Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.

Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.

Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.

Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.

Abstract: A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate having a bottom substrate, a buried oxide layer disposed on the bottom substrate, and a semiconductor layer disposed on the buried oxide layer. The semiconductor structure further includes a doped layer embedded in the semiconductor layer and above the buried oxide layer, and a contact structure extending into the semiconductor layer from the top surface of the semiconductor layer. The contact structure is electrically connected to the doped layer.

Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a semiconductor layer formed on the substrate. The semiconductor structure includes an isolation structure through the semiconductor layer, and the isolation structure has an opening with a first width, and the isolation structure has a vacuum gap. The semiconductor structure also includes a contact plug structure through the semiconductor layer, and the contact plug structure has an opening with a second width, and the second width is greater than the first width.

Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.

Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate having a bottom substrate, a buried oxide layer disposed on the bottom substrate, and a semiconductor layer disposed on the buried oxide layer. The semiconductor structure further includes a doped layer embedded in the semiconductor layer and above the buried oxide layer, and a contact structure extending into the semiconductor layer from the top surface of the semiconductor layer. The contact structure is electrically connected to the doped layer.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor on an insulator (SOI) substrate having a bottom substrate, a buried oxide layer on the bottom substrate, and a semiconductor layer on the buried oxide layer. The semiconductor device also includes a first dielectric layer disposed on the semiconductor layer, a first contact structure extending from a top surface of the first dielectric layer through the semiconductor layer and the buried oxide layer and contacting the bottom substrate, and a first trench extending into the semiconductor layer. A width of the first trench is smaller than a width of the first contact structure. The first dielectric layer seals the first trench at or near the top of the first trench to form a vacuum gap.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a semiconductor layer formed on the substrate. The semiconductor structure includes an isolation structure through the semiconductor layer, and the isolation structure has an opening with a first width, and the isolation structure has a vacuum gap. The semiconductor structure also includes a contact plug structure through the semiconductor layer, and the contact plug structure has an opening with a second width, and the second width is greater than the first width.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor on an insulator (SOI) substrate having a bottom substrate, a buried oxide layer on the bottom substrate, and a semiconductor layer on the buried oxide layer. The semiconductor device also includes a first dielectric layer disposed on the semiconductor layer, a first contact structure extending from a top surface of the first dielectric layer through the semiconductor layer and the buried oxide layer and contacting the bottom substrate, and a first trench extending into the semiconductor layer. A width of the first trench is smaller than a width of the first contact structure. The first dielectric layer seals the first trench at or near the top of the first trench to form a vacuum gap.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer disposed over the substrate; a gate electrode disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate electrode; a trench extending from a top surface of the epitaxial layer through the source region into the epitaxial layer, wherein the trench has a slanted side and a bottom surface; and a first conductive-type linking region having the first conductive type, wherein the first conductive-type linking region surrounds the slanted side of the trench and contacts the bottom surface of the trench, wherein the first conductive-type linking region electrically connects the source region and the substrate. The present disclosure also provides a method for manufacturing this semiconductor device.

Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.

Abstract: A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

Abstract: A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction.

Abstract: A composite integrated circuit (IC) includes a first circuit layer, a second circuit layer having a first chip and a second chip, and a first wireless power transfer (WPT) device in the first chip or the first circuit layer. The first WPT device generates a power supply voltage by extracting energy from an electromagnetic signal. A first tracking circuit in the second chip or the first circuit layer is powered by the power supply voltage from the first WPT device and stores or outputs tracking data in response to an instruction extracted from the electromagnetic signal.

Abstract: A lateral double diffused metal-oxide-semiconductor device includes: an epitaxial semiconductor layer disposed over a semiconductor substrate; a gate dielectric layer disposed over the epitaxial semiconductor layer; a gate stack disposed over the gate dielectric layer; a first doped region disposed in the epitaxial semiconductor layer from a first side of the gate stack; a second doped region disposed in the epitaxial semiconductor layer from a second side of the gate stack; a third doped region disposed in the first doping region; a fourth doped region disposed in the second doped region; an insulating layer covering the third doped region, the gate dielectric layer, and the gate stack; a conductive contact disposed in the insulating layer, the third doped region, the first doped region and the epitaxial semiconductor layer; and a fifth doped region disposed in the epitaxial semiconductor layer under the conductive contact.