Abstract: A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

Abstract: A circuit and a method are disclosed herein. The circuit includes a digitally controlled oscillator and a detector. The digitally controlled oscillator is configured to generate an oscillator signal according to an oscillator tuning word. The detector is configured to output one of a first control word and a second control word that is derived from the first control word as the oscillator tuning word.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer disposed over the substrate; a gate electrode disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate electrode; a trench extending from a top surface of the epitaxial layer through the source region into the epitaxial layer, wherein the trench has a slanted side and a bottom surface; and a first conductive-type linking region having the first conductive type, wherein the first conductive-type linking region surrounds the slanted side of the trench and contacts the bottom surface of the trench, wherein the first conductive-type linking region electrically connects the source region and the substrate. The present disclosure also provides a method for manufacturing this semiconductor device.

Abstract: A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction.

Abstract: A circuit and a method are disclosed herein. The circuit includes a digitally controlled oscillator and a detector. The digitally controlled oscillator is configured to generate an oscillator signal according to an oscillator tuning word. The detector is configured to output one of a first control word and a second control word that is derived from the first control word as the oscillator tuning word.

Abstract: A computer system includes a processor and a computer-readable storage medium. The computer-readable storage medium has stored therein instructions that when executed by the processor perform a method for generating initial cluster centroids. The method includes generating (Key1, Value1) pairs of input datasets. The method also includes calculating global designated values, among the generated (Key1, Value1) pairs, to be reference values. The method also includes calculating similarity values of the input datasets based on the reference values. The method further includes generating (Key2, Value2) pairs of input datasets. The method further includes generating median similarity value, among the generated (Key2, Value2) pairs, to generate corresponding initial cluster centroids. The Key1 and the Value1 are a feature variable and a feature value, respectively, of corresponding input dataset. The Key2 and the Value2 are the similarity value and the feature value, respectively, of corresponding input dataset.

Abstract: A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction.

Abstract: A semiconductor wafer includes a plurality of dies and at least one test probe. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit. The at least one test probe includes a plurality of probe pads. The plurality of probe pads is configured to transmit power signals and data to each of the plurality of dies, and to receive test results from each of the plurality of dies. The data are transmitted to each of the plurality of dies in a serial manner. The test results of each of the plurality of dies are also transmitted to the plurality of probe pads in a serial manner.

Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.

Abstract: A semiconductor device includes a semiconductor layer, a plurality of first doped regions, a gate structure, and second and third doped regions. The semiconductor layer has a first conductivity type. The first doped regions are in parallel disposed in a portion of the semiconductor layer along a first direction and have a second conductivity type and a rectangular top view. The gate structure is disposed over a portion of the semiconductor layer along a second direction, covering a portion of the first doped regions. The second doped region is disposed in the semiconductor layer along the second direction, being adjacent to a first side of the gate structure and having the second conductivity type. The third doped region is formed in the semiconductor layer along the second direction, being adjacent to a second side of the gate structure opposing the first side and having the second conductivity type.

Abstract: A semiconductor device includes: a semiconductor layer having an active region defined thereover, wherein the active region comprises a first sub-region and a second sub-region; a first doped region disposed in a portion of the semiconductor layer, extending across the first sub-region and the second sub-region; a high-voltage (HV) semiconductor element disposed over the semiconductor layer in the first sub-region, wherein the HV semiconductor element comprises a portion of the first doped region formed in the semiconductor layer in the first-sub region of the active region; and an electrostatic discharge (ESD) protection element disposed over the semiconductor layer in the second sub-region, wherein the ESD protection element comprises the other portion of the doped region formed in the semiconductor layer in the second sub-region of the active region.

Abstract: A composite integrated circuit (IC) includes a first circuit layer, a second circuit layer having a first chip and a second chip, and a first wireless power transfer (WPT) device in the first chip or the first circuit layer. The first WPT device generates a power supply voltage by extracting energy from an electromagnetic signal. A first tracking circuit in the second chip or the first circuit layer is powered by the power supply voltage from the first WPT device and stores or outputs tracking data in response to an instruction extracted from the electromagnetic signal.

Abstract: A lateral double diffused metal-oxide-semiconductor device includes: a semiconductor substrate; an epitaxial semiconductor layer disposed over the semiconductor substrate; a gate structure disposed over the epitaxial semiconductor layer; a first doped region disposed in the epitaxial semiconductor layer at a first side of the gate structure; a second doped region disposed in the epitaxial semiconductor layer at a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the epitaxial semiconductor layer under the first doped region; a conductive contact formed in the trench; and a fifth doped region disposed in the epitaxial semiconductor layer under the trench.

Abstract: A semiconductor device includes a semiconductor layer, a plurality of first doped regions, a gate structure, and second and third doped regions. The semiconductor layer has a first conductivity type. The first doped regions are in parallel disposed in a portion of the semiconductor layer along a first direction and have a second conductivity type and a rectangular top view. The gate structure is disposed over a portion of the semiconductor layer along a second direction, covering a portion of the first doped regions. The second doped region is disposed in the semiconductor layer along the second direction, being adjacent to a first side of the gate structure and having the second conductivity type. The third doped region is formed in the semiconductor layer along the second direction, being adjacent to a second side of the gate structure opposing the first side and having the second conductivity type.

Abstract: A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction.

Abstract: A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period.

Abstract: A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

Abstract: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.

Abstract: A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.

Abstract: A method for fabricating a semiconductor device is provided. A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first conductive type. An epitaxy layer having the first conductive type is formed on the semiconductor substrate. First trenches are formed in the epitaxy layer. First insulating liner layers are formed on sidewalls and bottoms of the first trenches. A first dopant having the first conductive type dopes the epitaxy layer from the sidewalls of the first trenches to form first doped regions. A first insulating material is filled into the first trenches. Second trenches are formed in the epitaxy layer. Second insulating liner layers are formed on sidewalls and bottoms of the second trenches. A second dopant having a second conductive type dopes the epitaxy layer from the sidewalls of the second trenches to form second doped regions.