Patents by Inventor Tsung-Hung Lee
Tsung-Hung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107691Abstract: A display device includes first and second display modules and first and second turning pieces that include a first coupling piece, a first turning piece, a second turning piece, and a third turning piece, a second coupling piece and a guiding device. When the first and second display modules are switched between folding and unfolding, the first turning piece pivots relative to the first coupling piece and the second turning piece, and the third turning piece pivots relative to the second coupling piece and the second turning piece. When the display module is switched from folded to unfolded, the other side of the first display module relative to the side is pulled, the side of the first display module is guided by one end of the guiding device and slides to the other end, the first and second display modules are symmetrically unfolded with the side edge as the center.Type: ApplicationFiled: December 8, 2023Publication date: March 28, 2024Inventors: CHIEN-FENG CHANG, TSUNG-HUAI LEE, YU-HUNG HSIAO, CHAN-PENG LIN, SHANG-CHIEN WU
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Patent number: 11935795Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.Type: GrantFiled: July 28, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
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Publication number: 20230326802Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.Type: ApplicationFiled: June 5, 2023Publication date: October 12, 2023Inventors: Szu-Chi Yang, Allen Chien, Tsai-Yu Huang, Chien-Chih Lin, Po-Kai Hsiao, Shih-Hao Lin, Chien-Chih Lee, Chih Chieh Yeh, Cheng-Ting Ding, Tsung-Hung Lee
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Patent number: 11670551Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.Type: GrantFiled: July 10, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Chi Yang, Allen Chien, Cheng-Ting Ding, Chien-Chih Lin, Chien-Chih Lee, Shih-Hao Lin, Tsung-Hung Lee, Chih Chieh Yeh, Po-Kai Hsiao, Tsai-Yu Huang
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Publication number: 20220123126Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.Type: ApplicationFiled: January 3, 2022Publication date: April 21, 2022Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
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Patent number: 11217679Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.Type: GrantFiled: April 1, 2020Date of Patent: January 4, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
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Publication number: 20210313441Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
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Publication number: 20210098305Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.Type: ApplicationFiled: July 10, 2020Publication date: April 1, 2021Inventors: Szu-Chi Yang, Allen Chien, Cheng-Ting Ding, Chien-Chih Lin, Chien-Chih Lee, Shih-Hao Lin, Tsung-Hung Lee, Chih Chieh Yeh, Po-Kai Hsiao, Tsai-Yu Huang
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Patent number: 10963042Abstract: The blinking control method comprises the following steps. First, detect a current blinking signal, wherein the current blinking signal occurs at a current blinking time point. Afterwards, obtain a predicted spontaneous blinking time slot according to the current blinking time point, a minimum spontaneous blinking calibration time interval, and a maximum spontaneous blinking calibration time interval. Afterwards, detect a next blinking signal. Afterwards, determine if the next blinking signal occurs within the predicted spontaneous blinking time slot. Determine if the next blinking signal belongs to a spontaneous blinking when the next blinking signal occurs within the predicted spontaneous blinking time slot. Determine if the next blinking signal belongs to a controlled blinking when the next blinking signal occurs outside the predicted spontaneous blinking time slot.Type: GrantFiled: September 5, 2019Date of Patent: March 30, 2021Assignee: Qisda CorporationInventors: Tsung-Hung Lee, Wei-Huan Lee
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Patent number: 10893205Abstract: An image display method and an image display device using the same are provided. The image display method includes the following steps. Firstly, a picture is obtained. Then, the content of the part of the picture corresponding to the characteristic parameter is captured as an object image when the content of the picture matches a characteristic parameter. Then, the object image is captured as a click image. Then, the first display portion of the picture is displayed and the click image is superimposed on the first display portion. Then, the second display portion of the picture is displayed in response to the operation of selecting the superimposed click image, wherein the second display portion contains the object image and a background image thereof. Thus, through the selection with respect to the click image, the display device switches the display frame to a frame with object image.Type: GrantFiled: May 6, 2019Date of Patent: January 12, 2021Assignee: Qisda CorporationInventors: Tsung-Hung Lee, Wei-Huan Lee
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Publication number: 20200103960Abstract: The blinking control method comprises the following steps. First, detect a current blinking signal, wherein the current blinking signal occurs at a current blinking time point. Afterwards, obtain a predicted spontaneous blinking time slot according to the current blinking time point, a minimum spontaneous blinking calibration time interval, and a maximum spontaneous blinking calibration time interval. Afterwards, detect a next blinking signal. Afterwards, determine if the next blinking signal occurs within the predicted spontaneous blinking time slot. Determine if the next blinking signal belongs to a spontaneous blinking when the next blinking signal occurs within the predicted spontaneous blinking time slot. Determine if the next blinking signal belongs to a controlled blinking when the next blinking signal occurs outside the predicted spontaneous blinking time slot.Type: ApplicationFiled: September 5, 2019Publication date: April 2, 2020Applicant: Qisda CorporationInventors: Tsung-Hung LEE, Wei-Huan LEE
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Publication number: 20190387177Abstract: An image display method and an image display device using the same are provided. The image display method includes the following steps. Firstly, a picture is obtained. Then, the content of the part of the picture corresponding to the characteristic parameter is captured as an object image when the content of the picture matches a characteristic parameter. Then, the object image is captured as a click image. Then, the first display portion of the picture is displayed and the click image is superimposed on the first display portion. Then, the second display portion of the picture is displayed in response to the operation of selecting the superimposed click image, wherein the second display portion contains the object image and a background image thereof. Thus, through the selection with respect to the click image, the display device switches the display frame to a frame with object image.Type: ApplicationFiled: May 6, 2019Publication date: December 19, 2019Applicant: Qisda CorporationInventors: Tsung-Hung LEE, Wei-Huan LEE
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Patent number: 9659776Abstract: First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.Type: GrantFiled: May 12, 2016Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Kai Chen, Tsung-Hung Lee, Han-Pin Chung, Shih-Syuan Huang, Chun-Fu Cheng, Chien-Tai Chan, Kuang-Yuan Hsu, Hsien-Chin Lin, Ka-Hing Fung
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Publication number: 20160260610Abstract: First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.Type: ApplicationFiled: May 12, 2016Publication date: September 8, 2016Inventors: Hung-Kai Chen, Tsung-Hung Lee, Han-Pin Chung, Shih-Syuan Huang, Chun-Fu Cheng, Chien-Tai Chan, Kuang-Yuan Hsu, Hsien-Chin Lin, Ka-Hing Fung
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Patent number: 9362404Abstract: First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.Type: GrantFiled: February 21, 2014Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Kai Chen, Tsung-Hung Lee, Han-Pin Chung, Shih-Syuan Huang, Chun-Fu Cheng, Chien-Tai Chan, Kuang-Yuan Hsu, Hsien-Chin Lin, Ka-Hing Fung
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Publication number: 20150243739Abstract: First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.Type: ApplicationFiled: February 21, 2014Publication date: August 27, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Kai Chen, Tsung-Hung Lee, Han-Pin Chung, Shih-Syuan Huang, Chun-Fu Cheng, Chien-Tai Chan, Kuang-Yuan Hsu, Hsien-Chin Lin, Ka-Hing Fung
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Patent number: 8982030Abstract: A gate output control method is adapted into a flat display having a plurality of gate drive integrated circuits. The method comprises: providing a gate control signal; providing a oblique control signal to oblique modulate the gate control signal for generating a gate control signal with oblique; modulating the gate control signal with oblique to obtain a modulated gate control signal; and outputting the modulated gate control signal to the gate drive integrated circuits. A falling edge of the modulated gate control signal comprises a oblique-varying period and a vertical-varying period. In the oblique-varying period, the modulated gate control signal firstly changes to a predetermined voltage in a first slope, and then changes in a second slope until the vertical-varying period. In the vertical-varying period, the modulated gate control signal changes vertically or nearly vertically.Type: GrantFiled: July 15, 2010Date of Patent: March 17, 2015Assignee: AU Optronics Corp.Inventors: Kai-Yuan Siao, Jian-Feng Li, Hsiao-Chung Cheng, Tsung-Hung Lee, Chao-Ching Hsu
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Patent number: 8562163Abstract: A power transmission circuit, a light source module including the power transmission circuit, and a panel display device are provided. The power transmission circuit includes a substrate, a power transmission layer, a metal shielding layer, a first protective layer, and a second protective layer. The substrate has a first surface and a second surface with the power transmission layer and the metal shielding layer respectively formed thereon. The metal shielding layer covers a projection region of a transmission section of the power transmission layer. The first and second protective layers are respectively disposed on the power transmission layer and the metal shielding layer and opposite to the substrate to protect the power transmission layer and the metal shielding layer.Type: GrantFiled: February 17, 2011Date of Patent: October 22, 2013Assignee: Au Optronics CorporationInventors: Chun-Hsien Lin, Tsung-Hung Lee, Chih-Liang Pan
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Patent number: 8278196Abstract: The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer.Type: GrantFiled: July 21, 2010Date of Patent: October 2, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lien Huang, Mao-Rong Yeh, Chun Hsiung Tsai, Tsung-Hung Lee, Da-Wen Lin, Tsz-Mei Kwok
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Patent number: 8106873Abstract: The present invention relates to a gate pulse modulation (GPM) circuit and the application of same in a liquid crystal display for improving the display performance thereof. The gate pulse modulation circuit is configured to modulate multi-phase clock pulse signals so as to correspondingly generate odd gate pulse waveforms and even gate pulse waveforms that are different from one another.Type: GrantFiled: July 20, 2009Date of Patent: January 31, 2012Assignee: AU Optronics CorporationInventors: Hsiao-Chung Cheng, Tsung-Hung Lee, Cin-Shun Chen