Patents by Inventor Tsung-Jen Liao
Tsung-Jen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079053Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
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Patent number: 11527499Abstract: An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.Type: GrantFiled: February 4, 2021Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tsui-Mei Chen, Tsung-Jen Liao, Li-Huan Chu, Pei-Haw Tsao
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Publication number: 20220352103Abstract: An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Inventors: Tsui-Mei CHEN, Tsung-Jen LIAO, Li-Huan CHU, Pei-Haw TSAO
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Publication number: 20210343667Abstract: An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.Type: ApplicationFiled: February 4, 2021Publication date: November 4, 2021Inventors: Tsui-Mei CHEN, Tsung-Jen LIAO, Li-Huan CHU, Pei-Haw TSAO
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Patent number: 11164764Abstract: The current disclosure describes carrier tape systems that include a carrier tape substrate and a cover tape. The carrier tape system includes a plurality of repetitive adhesion areas where the carrier tape substrate and cover tape are attached to each other and non-adhesion areas where the carrier tape substrate and cover tape are not attached to each other. Separating the cover tape and the carrier tape substrate at these repetitive adhesion and non-adhesion areas imparts a vibration to the cover tape which impedes or prevents semiconductor devices carried in pockets of the carrier tape substrate from adhering to adhesive on the cover tape.Type: GrantFiled: May 7, 2020Date of Patent: November 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Jen Liao, Pei-Haw Tsao, Tsui-Mei Chen
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Patent number: 11164763Abstract: The current disclosure describes carrier tape systems that include a carrier tape substrate and a cover tape. The carrier tape system includes a plurality of repetitive adhesion areas where the carrier tape substrate and cover tape are attached to each other and non-adhesion areas where the carrier tape substrate and cover tape are not attached to each other. Separating the cover tape and the carrier tape substrate at these repetitive adhesion and non-adhesion areas imparts a vibration to the cover tape which impedes or prevents semiconductor devices carried in pockets of the carrier tape substrate from adhering to adhesive on the cover tape.Type: GrantFiled: May 7, 2020Date of Patent: November 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Jen Liao, Pei-Haw Tsao, Tsui-Mei Chen
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Patent number: 10879098Abstract: The various embodiments provide a semiconductor chip holder that holds semiconductor chips. The chip holder protects the semiconductor chips from possible damage during transport and/or storage. The chip holder is flexible and may be wound around a reel for convenient transport and storage. In one embodiment, the chip holder includes a support substrate with receptacles that receive semiconductor chips, a cover layer that seals the receptacles and holds the semiconductor chips within the receptacles, and plugs to securely couple the support substrate and the cover layer together.Type: GrantFiled: September 18, 2018Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Jen Liao, Pei-Haw Tsao, Tsui-Mei Chen, Yu-Jung Lin, Ju-Min Chen, Sean Lin
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Publication number: 20200266082Abstract: The current disclosure describes carrier tape systems that include a carrier tape substrate and a cover tape. The carrier tape system includes a plurality of repetitive adhesion areas where the carrier tape substrate and cover tape are attached to each other and non-adhesion areas where the carrier tape substrate and cover tape are not attached to each other. Separating the cover tape and the carrier tape substrate at these repetitive adhesion and non-adhesion areas imparts a vibration to the cover tape which impedes or prevents semiconductor devices carried in pockets of the carrier tape substrate from adhering to adhesive on the cover tape.Type: ApplicationFiled: May 7, 2020Publication date: August 20, 2020Inventors: Tsung-Jen LIAO, Pei-Haw TSAO, Tsui-Mei CHEN
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Publication number: 20200266083Abstract: The current disclosure describes carrier tape systems that include a carrier tape substrate and a cover tape. The carrier tape system includes a plurality of repetitive adhesion areas where the carrier tape substrate and cover tape are attached to each other and non-adhesion areas where the carrier tape substrate and cover tape are not attached to each other. Separating the cover tape and the carrier tape substrate at these repetitive adhesion and non-adhesion areas imparts a vibration to the cover tape which impedes or prevents semiconductor devices carried in pockets of the carrier tape substrate from adhering to adhesive on the cover tape.Type: ApplicationFiled: May 7, 2020Publication date: August 20, 2020Inventors: Tsung-Jen LIAO, Pei-Haw TSAO, Tsui-Mei CHEN
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Patent number: 10679877Abstract: The current disclosure describes carrier tape systems that include a carrier tape substrate and a cover tape. The carrier tape system includes a plurality of repetitive adhesion areas where the carrier tape substrate and cover tape are attached to each other and non-adhesion areas where the carrier tape substrate and cover tape are not attached to each other. Separating the cover tape and the carrier tape substrate at these repetitive adhesion and non-adhesion areas imparts a vibration to the cover tape which impedes or prevents semiconductor devices carried in pockets of the carrier tape substrate from adhering to adhesive on the cover tape.Type: GrantFiled: March 28, 2019Date of Patent: June 9, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Jen Liao, Pei-Haw Tsao, Tsui-Mei Chen
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Publication number: 20200090970Abstract: The various embodiments provide a semiconductor chip holder that holds semiconductor chips. The chip holder protects the semiconductor chips from possible damage during transport and/or storage. The chip holder is flexible and may be wound around a reel for convenient transport and storage. In one embodiment, the chip holder includes a support substrate with receptacles that receive semiconductor chips, a cover layer that seals the receptacles and holds the semiconductor chips within the receptacles, and plugs to securely couple the support substrate and the cover layer together.Type: ApplicationFiled: September 18, 2018Publication date: March 19, 2020Inventors: Tsung-Jen Liao, Pei-Haw Tsao, Tsui-Mei Chen, Yu-Jung Lin, Ju-Min Chen, Sean Lin
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Publication number: 20200006098Abstract: The current disclosure describes carrier tape systems that include a carrier tape substrate and a cover tape. The carrier tape system includes a plurality of repetitive adhesion areas where the carrier tape substrate and cover tape are attached to each other and non-adhesion areas where the carrier tape substrate and cover tape are not attached to each other. Separating the cover tape and the carrier tape substrate at these repetitive adhesion and non-adhesion areas imparts a vibration to the cover tape which impedes or prevents semiconductor devices carried in pockets of the carrier tape substrate from adhering to adhesive on the cover tape.Type: ApplicationFiled: March 28, 2019Publication date: January 2, 2020Inventors: Tsung-Jen LIAO, Pei-Haw TSAO, Tsui-Mei CHEN
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Patent number: 9576820Abstract: A method of manufacturing a chip fan-out structure, said method includes forming a dry film with a predetermined pattern. Providing a chip wherein the distribution of the pad is corresponding to the dry film's predetermined pattern. Contacting the surface of the pad with the dry film. Forming a molding compound to encapsulate the chip, and removing the dry film to expose the pads.Type: GrantFiled: March 18, 2013Date of Patent: February 21, 2017Assignee: CHIPMOS TECHNOLOGIES INCInventor: Tsung Jen Liao
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Patent number: 9437542Abstract: A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit layer. The chip includes an active surface, a back surface opposite to the active surface. The inducting coil is disposed around a periphery region of the chip. The molding compound covers the chip and the periphery region and exposes the active surface. The inducting coil is disposed at the molding compound. The redistribution circuit layer covers the active surface, part of the molding compound and part of the inducting coil, and electrically connects the chip.Type: GrantFiled: December 31, 2015Date of Patent: September 6, 2016Assignee: ChipMOS Technologies Inc.Inventor: Tsung-Jen Liao
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Publication number: 20160111364Abstract: A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit layer. The chip includes an active surface, a back surface opposite to the active surface. The inducting coil is disposed around a periphery region of the chip. The molding compound covers the chip and the periphery region and exposes the active surface. The inducting coil is disposed at the molding compound. The redistribution circuit layer covers the active surface, part of the molding compound and part of the inducting coil, and electrically connects the chip.Type: ApplicationFiled: December 31, 2015Publication date: April 21, 2016Inventor: Tsung-Jen Liao
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Patent number: 9269643Abstract: A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit layer. The chip includes an active surface, a back surface opposite to the active surface. The inducting coil is disposed around a periphery region of the chip. The molding compound covers the chip and the periphery region and exposes the active surface. The inducting coil is disposed at the molding compound. The redistribution circuit layer covers the active surface, part of the molding compound and part of the inducting coil, and electrically connects the chip.Type: GrantFiled: July 7, 2014Date of Patent: February 23, 2016Assignee: ChipMOS Technologies Inc.Inventor: Tsung-Jen Liao
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Patent number: 9196553Abstract: A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer.Type: GrantFiled: January 18, 2012Date of Patent: November 24, 2015Assignee: ChipMOS Technologies Inc.Inventors: Tsung-Jen Liao, Mei-Fang Peng, Cheng-Tang Huang
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Patent number: 9190324Abstract: A manufacturing method for a micro bump structure includes the following steps as follows. A substrate is provided and a under bump metallurgy (UBM) is formed on the substrate for accommodating a solder ball. A buffer layer is disposed on the substrate and then the solder ball is disposed on the UBM. Finally, the solder ball is grinded in order get the height reduced to a predetermined height.Type: GrantFiled: April 2, 2013Date of Patent: November 17, 2015Assignee: CHIPMOS TECHNOLOGIES INC.Inventor: Tsung Jen Liao
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Patent number: 9123684Abstract: A chip package structure including a leadframe, a chip, at least one heat dissipation pillar, and a molding compound is provided. The leadframe includes a die pad and a plurality of leads. The die pad has at least one through hole. The leads surround the die pad. The chip is located on the die pad and electronically connected to the leads. The chip includes an active surface and a back surface opposite to the active surface. The back surface of the chip is adhered to the die pad. The heat dissipation pillar is located on the back surface and passes through the through hole. The molding compound encapsulates the chip, at least parts of the leads, and the die pad. The molding compound includes at least one opening to expose the heat dissipation pillar. A manufacturing method of the chip package structure is also provided.Type: GrantFiled: June 15, 2014Date of Patent: September 1, 2015Assignee: ChipMOS Technologies Inc.Inventor: Tsung-Jen Liao
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Patent number: 9087912Abstract: The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.Type: GrantFiled: March 5, 2014Date of Patent: July 21, 2015Assignee: CHIPMOS TECHNOLOGIES INC.Inventor: Tsung Jen Liao