Abstract: A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit layer. The chip includes an active surface, a back surface opposite to the active surface. The inducting coil is disposed around a periphery region of the chip. The molding compound covers the chip and the periphery region and exposes the active surface. The inducting coil is disposed at the molding compound. The redistribution circuit layer covers the active surface, part of the molding compound and part of the inducting coil, and electrically connects the chip.

Abstract: A chip package structure including a leadframe, a chip, at least one heat dissipation pillar, and a molding compound is provided. The leadframe includes a die pad and a plurality of leads. The die pad has at least one through hole. The leads surround the die pad. The chip is located on the die pad and electronically connected to the leads. The chip includes an active surface and a back surface opposite to the active surface. The back surface of the chip is adhered to the die pad. The heat dissipation pillar is located on the back surface and passes through the through hole. The molding compound encapsulates the chip, at least parts of the leads, and the die pad. The molding compound includes at least one opening to expose the heat dissipation pillar. A manufacturing method of the chip package structure is also provided.

Abstract: A fan-out package structure including a heat radiating side edge that includes a semiconductor substrate; a bond pad located on the semiconductor substrate; and a redistribution layer connected with the bond pad and located on the semiconductor substrate, wherein an end of the redistribution layer extends to a sidewall of the semiconductor substrate, and the end is coplanar with the sidewall.

Abstract: The present disclosure relates to a package structure of a lead frame. The package includes a die, a dielectric layer, at least one conducting pillar, at least one lead frame and at least one solder ball. The dielectric layer is disposed on a surface of the die. The at least one conducting pillar penetrates through the dielectric layer and is disposed on the surface. The at least one lead frame is disposed on the dielectric layer and is spaced from the at least one conducting pillar with a gap. The solder ball fills the gap and electrically connects the at least one conducting pillar and the at least one lead frame.

Abstract: A chip structure and a multi-chip stack package are provided. The chip structure includes a chip, at least one interlink plate and a plurality of first connection terminals. The chip has an active surface, a back surface opposite to the active surface and a plurality of side surfaces respectively connected to the active surface and the back surface. The chip includes at least one bond pad disposed on the active surface and at least one joint pad disposed on the back surface. The interlink plate substantially parallel to one of the side surfaces includes a base and a conductive pattern disposed on the base. The conductive pattern is located between the base and the chip. The first connection terminals are disposed between the chip and the interlink plate. The bond pad is electrically connected to the joint pad through the first connection terminals and the conductive pattern.

Abstract: The present invention provides a method for manufacturing a semiconductor package structure, including (i) providing a carrier plate; (ii) disposing a die on the carrier plate; (iii) forming a plurality of bonding wires having a first end and a second end; (iv) forming an encapsulant covering the die and the bonding wires and exposing a portion of each of the bonding wires from a first surface thereof; (v) removing the carrier plate; (vi) forming a patterned conductive layer on a second surface of the encapsulant opposite to the first surface; (vii) electrically connecting the second ends of the bonding wires to the active surface of the die via the patterned conductive layer; and (viii) forming a plurality of first external connection terminals on the first surface of the encapsulant respectively covering the portions of the bonding wires exposed from the encapsulant.

Abstract: The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.

Abstract: The present disclosure relates to a ball planting device for mounting a solder ball and a ball planting method thereof. The device includes a substrate, a dielectric layer, and a solder paste. The substrate includes a surface. The dielectric layer is disposed on the surface. The dielectric layer includes a plurality of apertures. The solder paste fills the apertures. A top surface of the solder paste is aligned with an exposed surface of the dielectric layer.

Abstract: The present invention provides a method for manufacturing a semiconductor package structure, including (i) providing a carrier plate; (ii) disposing a die on the carrier plate; (iii) forming a plurality of bonding wires having a first end and a second end; (iv) forming an encapsulant covering the die and the bonding wires and exposing a portion of each of the bonding wires from a first surface thereof; (v) removing the carrier plate; (vi) forming a patterned conductive layer on a second surface of the encapsulant opposite to the first surface; (vii) electrically connecting the second ends of the bonding wires to the active surface of the die via the patterned conductive layer; and (viii) forming a plurality of first external connection terminals on the first surface of the encapsulant respectively covering the portions of the bonding wires exposed from the encapsulant.

Abstract: The present invention provides a semiconductor package structure, which includes a die, a plurality of bonding wires, an encapsulant, and a plurality of first external terminals. The die has an active surface and a back surface. A first end of each of the bonding wires is connected to the back surface of the die, and a second end opposite to the first end is electrically connected to the active surface of the die. The encapsulant covers the back surface of the die and the bonding wires, wherein a portion of each of the bonding wires is exposed from the encapsulant. The first external terminals are disposed on the top surface of the encapsulant, and cover the exposed portions of the bonding wires respectively and are electrically connected to the bonding wires.

Abstract: A chip structure and a multi-chip stack package are provided. The chip structure includes a chip, at least one interlink plate and a plurality of first connection terminals. The chip has an active surface, a back surface opposite to the active surface and a plurality of side surfaces respectively connected to the active surface and the back surface. The chip includes at least one bond pad disposed on the active surface and at least one joint pad disposed on the back surface. The interlink plate substantially parallel to one of the side surfaces includes a base and a conductive pattern disposed on the base. The conductive pattern is located between the base and the chip. The first connection terminals are disposed between the chip and the interlink plate. The bond pad is electrically connected to the joint pad through the first connection terminals and the conductive pattern.

Abstract: A manufacturing method for a micro bump structure includes the following steps as follows. A substrate is provided and a under bump metallurgy (UBM) is formed on the substrate for accommodating a solder ball. A buffer layer is disposed on the substrate and then the solder ball is disposed on the UBM. Finally, the solder ball is grinded in order get the height reduced to a predetermined height.

Abstract: A semiconductor structure includes a semiconductor substrate, a metal layer formed on the semiconductor substrate, a conductive pillar, and a solder ball. The conductive pillar is formed on and electrically connected with the metal layer, wherein the conductive pillar has a bearing surface and a horizontal sectional surface under the bearing surface, and the contact surface area of the bearing surface is larger than the area of the horizontal sectional surface. The solder ball is located on the conductive pillar and covers the bearing surface.

Abstract: The present invention provides a semiconductor package structure, which includes a die, a plurality of bonding wires, an encapsulant, and a plurality of first external terminals. The die has an active surface and a back surface. A first end of each of the bonding wires is connected to the back surface of the die, and a second end opposite to the first end is electrically connected to the active surface of the die. The encapsulant covers the back surface of the die and the bonding wires, wherein a portion of each of the bonding wires is exposed from the encapsulant. The first external terminals are disposed on the top surface of the encapsulant, and cover the exposed portions of the bonding wires respectively and are electrically connected to the bonding wires.

Abstract: The present disclosure provides a semiconductor device including a semiconductor element having a first surface and a second surface, which is opposite to the first surface, and a conductive via disposed on the semiconductor element. The semiconductor element includes a die; a first redistribution layer positioned on the first surface, wherein the first redistribution layer is configured to fan out the die; and a second redistribution layer positioned on the second surface of the semiconductor element. The conductive via is configured to electrically connect the first redistribution layer and the second redistribution layer, wherein the sizes of the two ends of the conductive via are different and the die can be electrically coupled to another semiconductor device through the conductive via.

Abstract: A method of manufacturing a chip fan-out structure, said method includes forming a dry film with a predetermined pattern. Providing a chip wherein the distribution of the pad is corresponding to the dry film's predetermined pattern. Contacting the surface of the pad with the dry film. Forming a molding compound to encapsulate the chip, and removing the dry film to expose the pads.

Abstract: A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer.

Abstract: A method of manufacturing a semiconductor package structure is provided. A chip is provided. An active surface of the chip is disposed on a carrier. A molding compound is formed on the carrier with a metal layer disposed thereon. The metal layer has an upper and lower surface, multiple cavities formed on the upper surface and multiple protrusions formed on the lower surface and corresponding to the cavities. The protrusions are embedded in the molding compound. The metal layer is patterned to form multiple pads on a portion of the molding compound. The carrier and the molding compound are separated. Multiple through holes are formed on the molding compound exposing the protrusions. A redistribution layer is formed on the molding compound and the active surface of the chip. Multiple solder balls are formed on the redistribution layer. A portion of the solder balls are correspondingly disposed to the pads.

Abstract: A light emitting diode module includes: a printed circuit board including an upper circuit layer, a lower metal layer, an insulating layer, and a plurality of through holes; a metallic heat sink formed with a plurality of chip-support portions and disposed below the printed circuit board; a thermal connection layer that has lower and upper surfaces respectively bonded to the heat sink and the lower metal layer of the printed circuit board; and a plurality of light emitting diode chips, each of which is placed in contact with and bonded to one of the chip-support portions and each of which is electrically connected to the upper circuit layer. A method for making the light emitting diode module is also disclosed.

Abstract: A planar light source device includes: a substrate having a thickness larger than 0.9 mm and including a metal layer; and a plurality of light-emitting diode chips disposed on the substrate in a matrix array. Each light-emitting diode chip has a chip size ranging from 0.0784 mm2 to 0.25 mm2. Two adjacent ones of the light-emitting diode chips are spaced apart from each other by a distance of at least two times a length of the light-emitting diode chips.