Patents by Inventor Tsung Li
Tsung Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145398Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.Type: ApplicationFiled: December 8, 2022Publication date: May 2, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Cheng-Liang HSU, Wan-Rou CHEN, Hsin-Yin CHANG, Tsung-Li LIN, Hsiu-Jung LI, Chiu-Lien LI, Fu-Quan XU, Yi-Wen LIU, Chih-Chieh SUN
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Patent number: 11962693Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.Type: GrantFiled: December 9, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
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Patent number: 11956939Abstract: A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.Type: GrantFiled: March 14, 2023Date of Patent: April 9, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tsung-Sheng Kang, Ardasheir Rahman, Tao Li, Albert M. Young
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Patent number: 11947251Abstract: An illumination system provides an illumination beam and includes a red light source, a green light source, a blue light source, a first supplementary light source, a first X-shaped light-splitting assembly, a first light-splitting element, and a light-uniforming element. The red light source provides a red beam. The green light source provides a green beam. The blue light source provides a blue beam. The first supplementary light source provides a first supplementary beam. The first X-shaped light-splitting assembly guides the first supplementary beam and the blue beam to the first light-splitting element. The first light-splitting element guides the red beam, the green beam, the blue beam, and the first supplementary beam to the light-uniforming element. The first supplementary beam is a red supplementary beam or a blue supplementary beam, and the illumination system includes at least five light-emitting elements. A projection apparatus including the above illumination system is also provided.Type: GrantFiled: March 23, 2022Date of Patent: April 2, 2024Assignee: Coretronic CorporationInventors: Chi-Fu Liu, Tsung-Hsin Liao, Chun-Li Chen, Hung-Yu Lin
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Patent number: 11942424Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.Type: GrantFiled: December 1, 2021Date of Patent: March 26, 2024Assignee: International Business Machines CorporationInventors: Tao Li, Ruilong Xie, Tsung-Sheng Kang, Chih-Chao Yang
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Publication number: 20240096978Abstract: A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Inventors: Tsung-Sheng Kang, Tao Li, Ruilong Xie, Chih-Chao Yang
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COMPOSITIONS AND METHODS FOR PREPARING NUCLEIC ACID NANOSTRUCTURES USING COMPACTION OLIGONUCLEOTIDES
Publication number: 20240084380Abstract: The present disclosure provides compositions and related methods, e.g., for preparing immobilized nucleic acid nanostructures using compaction oligonucleotides. In some embodiments, rolling circle amplification reaction can be conducted with compaction oligonucleotides on-support or in-solution to generate concatemer molecules having multiple copies of a polynucleotide unit arranged in tandem. Each polynucleotide unit comprises a sequence-of-interest and at least one universal adaptor sequence that binds one end of a compaction oligonucleotide. The 5? and 3? regions of the compaction oligonucleotide can hybridize to the concatemer to pull together distal portions of the concatemer causing compaction of the concatemer to form a nanostructure. Nanostructures having tighter size and shape compared to concatemers generated in the absence of the compaction oligonucleotides.Type: ApplicationFiled: August 15, 2023Publication date: March 14, 2024Inventors: Sinan ARSLAN, Michael KIM, Ramreddy TIPANNA, Chunhong ZHOU, William LIGHT, Hua YU, Junhua ZHAO, Tsung-Li LIU -
Publication number: 20240088034Abstract: A microelectronic structure including a first nano device, where the first nano device includes a plurality of transistors. A bottom dielectric isolation located on the backside of each of the plurality of transistors of the first nano device. A separating dielectric layer located on the backside of the bottom dielectric isolation layer, where the separating dielectric layer is a continuous layer on the backside of each of the plurality of transistors of the first nano device.Type: ApplicationFiled: September 9, 2022Publication date: March 14, 2024Inventors: Tsung-Sheng Kang, Tao Li, Ruilong Xie, Chih-Chao Yang
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Publication number: 20240087861Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
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Patent number: 11929318Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.Type: GrantFiled: May 10, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Patent number: 11917340Abstract: A projection device, including an illumination system, a control element, a driving element, a light valve, and a projection lens, is provided. The illumination system includes multiple light sources for providing multiple light beams to be combined into an illumination light beam. The driving element respectively drives the light sources in a first mode or a second mode, so that the light beams have respective luminous brightness, and the driving element is switched from the first mode to the second mode according to a first signal. The control element provides the first signal to the driving element according to an optical state or a time state of the projection device. The light valve is adapted to convert the illumination light beam into an image light beam. The projection lens is adapted to project the image light beam out of the projection device.Type: GrantFiled: March 24, 2022Date of Patent: February 27, 2024Assignee: Coretronic CorporationInventors: Chi-Fu Liu, Tsung-Hsin Liao, Chun-Li Chen, Hung-Yu Lin
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Patent number: 11914436Abstract: An example system can include a noise sensor communicatively coupled to a controller of a computing device to dynamically determine a sound pressure level (SPL) of an environment in which the computing device is present. The computing device can include a cooling fan and the controller comprising a processor in communication with a memory resource including instructions executable to dynamically determine a threshold speed of the cooling fan based on the determined SPL of the environment set a speed of the cooling fan based on the determined threshold speed.Type: GrantFiled: September 4, 2019Date of Patent: February 27, 2024Assignee: Hewlett-Packard Development Company, L.P.Inventors: Hung-Wen Chang, Ai-Tsung Li, Shih-Han Chen
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Publication number: 20240060725Abstract: A cooling device includes a partitioning board abutting inner faces of two boards, respectively. A chamber is defined between the partitioning board and one of the two boards. Another chamber is defined between the partitioning board and another of the two boards and intercommunicates with the chamber via an intercommunication port and a backflow port of the partitioning board. A pump drives a working fluid to circulate in the two chambers. Two welding channels are formed on outer faces of the two boards and surround the two chambers, respectively. The smallest distance between a channel bottom face of each annular welding channel and the inner face of a respective board having the annular welding channel is smaller than that between the inner and outer faces of the respective board. The two boards are coupled to the partitioning board along the annular welding channels by laser welding.Type: ApplicationFiled: October 31, 2023Publication date: February 22, 2024Inventors: ALEX HORNG, MING-TSUNG LI, CHI-TING YEH
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Patent number: 11846470Abstract: A cooling device includes a partitioning board abutting inner faces of two boards, respectively. A chamber is defined between the partitioning board and one of the two boards. Another chamber is defined between the partitioning board and another of the two boards and intercommunicates with the chamber via an intercommunication port and a backflow port of the partitioning board. A pump drives a working fluid to circulate in the two chambers. Two welding channels are formed on outer faces of the two boards and surround the two chambers, respectively. The smallest distance between a channel bottom face of each annular welding channel and the inner face of a respective board having the annular welding channel is smaller than that between the inner and outer faces of the respective board. The two boards are coupled to the partitioning board along the annular welding channels by laser welding.Type: GrantFiled: August 20, 2021Date of Patent: December 19, 2023Assignee: SUNONWEALTH ELECTRIC MACHINE INDUSTRY CO., LTD.Inventors: Alex Horng, Ming-Tsung Li, Chi-Ting Yeh
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Patent number: 11800683Abstract: An immersion cooling system includes a sealed tank having a chamber. A circulating layer and a working layer are respectively formed by first and second working liquids filled in the chamber and are contiguous to each other. The boiling point of the second working liquid is higher than that of the first working liquid. The density of the second working liquid is lower than that of the first working liquid. The first and second working liquids do not dissolve in each other. A circulating cooling module includes a circulating pipeline having first and second ports located in the chamber. The circulating pipeline also has a heat absorbing section and a condensation section located between the first and second ports. The heat absorbing section is located in the working layer. The first working liquid flows into the circulating pipeline from the first port and circulates in the circulating pipeline.Type: GrantFiled: November 29, 2021Date of Patent: October 24, 2023Assignee: Sunonwealth Electric Machine Industry Co., Ltd.Inventors: Alex Horng, Tso-Kuo Yin, Ming-Tsung Li
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Publication number: 20230326065Abstract: Image data analysis, and particularly identifying cluster or polony locations for performing base-calling in a digital image of a flow cell during DNA sequencing is described. A method may include generating a first plurality of flow cell images of a cellular sample immobilized on a support by conducting one or more cycles of sequencing reactions. The cellular sample may include a plurality of concatemer molecules therewithin. For the first plurality of flow cell image, pixel intensities, and a respective color purity of each of the pixel intensities may be determined. A base calling template may include base calling locations based on the pixel intensities and the respective color purity of the pixel intensities. The base calling template may be for registering a second plurality of flow cell images of the support in one or more subsequent cycles of the one or more cycles.Type: ApplicationFiled: December 9, 2022Publication date: October 12, 2023Inventors: Connor THOMPSON, Tsung-li LIU, Semyon KRUGLYAK, Minghao GUO
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Patent number: 11754989Abstract: A semiconductor equipment management method applicable to an electronic device for managing multiple pieces of semiconductor equipment is provided. The pieces of semiconductor equipment are respectively controlled through multiple control hosts, and the control hosts and the electronic device are connected to a switch device. The method includes: receiving real-time image information of each control host through the switch device; determining whether the real-time image information of each control host includes a triggering event by performing an image recognition on the real-time image information; executing a macro corresponding to the triggering event, where the macro includes at least one self-defined operation; generating at least one input command according to the self-defined operation of the executed macro; and controlling the control hosts to execute the self-defined operation of the executed macro by transmitting the input command to the control hosts through the switch device.Type: GrantFiled: November 16, 2020Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sing-Tsung Li, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Chien-Ko Liao
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Publication number: 20230253195Abstract: A fabrication system for fabricating IC is provided. A processing tool includes at least one electrode and a RF sensor. The electrode is configured to receive a radio frequency (RF) signal from an RF signal generator during first and second semiconductor manufacturing processes. The RF sensor wirelessly detects intensity of the RF signal. A computation device extracts statistical characteristics with a sampling rate based on the detected intensity of the RF signal. A fault detection and classification (FDC) system includes a processor. The processor is configured to determine whether or not the detected intensity of the RF signal exceeds a threshold value or a threshold range according to the extracted statistical characteristics. When the detected intensity of the RF signal exceeds the threshold value or the threshold range, the processor notifies the processing tool to adjust the RF signal or stop tool to check parts damage.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Wun-Kai TSAI, Wen-Che LIANG, Chao-Keng LI, Zheng-Jie XU, Chih-Kuo CHANG, Sing-Tsung LI, Feng-Kuang WU, Hsu-Shui LIU
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Publication number: 20230230912Abstract: An electronic package is provided, which includes a substrate structure and an electronic element and a passive element disposed on the substrate structure, where a die placement area and a functional area separated from each other are defined on a surface of a substrate body of the substrate structure, so that a routing layer is arranged with linear conductive traces with a smaller width in the die placement area, and a sheet-shaped circuit with a larger width and electrically connected to the linear conductive traces is arranged in the functional area, so as to reduce a metal area on the surface of the substrate body, thereby avoiding the problem of warpage caused by stress concentration in the die placement area.Type: ApplicationFiled: December 8, 2022Publication date: July 20, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Wan-Rou CHEN, Yi-Wen LIU, Hsiu-Jung LI, Yi-Chen CHI, Tsung-Li LIN
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Publication number: 20230214493Abstract: A computer system for failing a secure boot in a case tampering event comprises a trusted platform module (TPM), for generating a plurality of random bytes for a secure boot of the computer system; a bootloader, for storing information in at least one hardware of the computer system and performing the secure boot, wherein the information comprises the plurality of random bytes, and the TPM is comprised in the bootloader; an operating system (OS), for performing the secure boot; and at least one sensor, for detecting a case tampering event in the computer system, and transmitting a signal for triggering a deletion of the plurality of random bytes, if the case tampering event happens in the computer system. The bootloader or the OS performs the operation of deleting the plurality of random bytes stored in the at least one hardware to fail the secure boot, in response to the signal.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: Moxa Inc.Inventors: YOONG TAK TAN, Chih-Yu Chen, Che-Yu Huang, Hsin-Ju Wu, Tsung-Yuan Wu, Tzung-Fu Tsai, Kuo-Chen Wu, Jian-Yu Liao, Tsung-Li Fang