Patents by Inventor Tsung-Lin Lee

Tsung-Lin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210184016
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain portion adjacent to the gate electrode, and a semiconductor layer between the gate electrode and the source/drain portion.
    Type: Application
    Filed: January 21, 2021
    Publication date: June 17, 2021
    Inventors: Chao-Ching CHENG, Wei-Sheng YUN, Shao-Ming YU, Tsung-Lin LEE, Chih-Chieh YEH
  • Patent number: 11031320
    Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
  • Patent number: 11018061
    Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai
  • Patent number: 10998442
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
  • Patent number: 10991811
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, Shao-Ming Yu, Tsung-Lin Lee, Chih-Chieh Yeh
  • Publication number: 20210119046
    Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Inventors: Wei-Jen Lai, Yen-Ming Chen, Tsung-Lin Lee
  • Publication number: 20210098599
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
  • Publication number: 20210098451
    Abstract: A semiconductor device includes a fin structure over a substrate. The fin structure includes a bottom portion and a top portion. The bottom and the top portions have different materials. The device also includes a liner layer on a sidewall of the bottom portion, a dielectric layer on side surfaces of the liner layer, an interfacial layer, and a gate structure over the dielectric layer and engages the fin structure. A top surface of the liner layer extends below a bottom surface of the top portion. The interfacial layer has a first section on and directly contacting sidewall surfaces of the bottom portion and a second section on and directly contacting top and sidewall surfaces of the top portion. The gate structure includes a high-k dielectric layer and a metal gate electrode over the high-k dielectric layer. The high-k dielectric layer directly contacts the first section of the interfacial layer.
    Type: Application
    Filed: July 24, 2020
    Publication date: April 1, 2021
    Inventors: Tsung-Chieh Hsiao, Johnson Chen, Tzung-Yi Tsai, Tsung-Lin Lee, Yen-Ming Chen
  • Publication number: 20210020517
    Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 21, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzung-Yi TSAI, Yen-Ming CHEN, Tsung-Lin LEE, Chih-Chieh YEH
  • Patent number: 10886268
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Chih Chieh Yeh, Tsung-Lin Lee, Yee-Chia Yeo, Meng-Hsuan Hsiao
  • Patent number: 10879240
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate. The fin structure includes a channel region, a portion of the channel region is made of silicon germanium (SiGe), and the silicon germanium (SiGe) has a gradient germanium (Ge) concentration. The FinFET device structure includes a gate structure formed on the channel region of the fin structure.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Wang, Zheng-Yang Pan, Shih-Chieh Chang, Yi-Min Huang, Shahaji B. More, Tsung-Lin Lee
  • Patent number: 10872893
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lin Yang, Chia-Cheng Ho, Chih Chieh Yeh, Cheng-Yi Peng, Tsung-Lin Lee
  • Patent number: 10868142
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
  • Patent number: 10861969
    Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Jen Lai, Yen-Ming Chen, Tsung-Lin Lee
  • Publication number: 20200365736
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 19, 2020
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
  • Publication number: 20200357914
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Chao-Ching CHENG, Chih Chieh YEH, Cheng-Hsien WU, Hung-Li CHIANG, Jung-Piao CHIU, Tzu-Chiang CHEN, Tsung-Lin LEE, Yu-Lin YANG, I-Sheng CHEN
  • Patent number: 10811318
    Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Chih-Chieh Yeh
  • Publication number: 20200290095
    Abstract: A method of forming a process film includes the following operations. A substrate is transferred into a process chamber having an interior surface. A process film is formed over the substrate, and the process film is also formed on the interior surface of the process chamber. The substrate is transferred out of the process chamber. A non-process film is formed on the interior surface of the process chamber. In some embodiments, porosity of the process film is greater than a porosity of the non-process film.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Lin Lee, Yi-Ming Lin, Chih-Hung Yeh, Zi-Yuang Wang
  • Patent number: 10727344
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Tsung-Lin Lee, Yu-Lin Yang, I-Sheng Chen
  • Patent number: 10720496
    Abstract: FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Tsung-Lin Lee