Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.

Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A superlattice structure includes a substrate. A first superlattice stack is disposed on the substrate. The first superlattice stack includes a first superlattice layer, a second superlattice layer and a third superlattice layer disposed from bottom to top. Three stress relaxation layers respectively disposed between the first superlattice layer and the second superlattice layer, the second superlattice layer and the third superlattice layer and on the third superlattice layer. Each of the stress relaxation layers includes a group III-V compound layer. The thickness of each of the stress relaxation layers should be greater than a relaxation critical thickness.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.

Abstract: A semiconductor structure includes a substrate including a device region, a peripheral region surrounding the device region, and a transition region disposed between the device region and the peripheral region. An epitaxial layer is disposed on the device region, the peripheral region, and the transition region. A first portion of the epitaxial layer on the peripheral region has a poly-crystal structure.

Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.

Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.

Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.