Patents by Inventor Tsung-Mu Yang
Tsung-Mu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11257939Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.Type: GrantFiled: December 12, 2019Date of Patent: February 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Yu-Chi Wang, Tsung-Mu Yang, Yu-Ren Wang
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Publication number: 20220045173Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.Type: ApplicationFiled: October 21, 2021Publication date: February 10, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Publication number: 20210249528Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.Type: ApplicationFiled: April 8, 2020Publication date: August 12, 2021Inventors: Yu-Ming Hsu, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Publication number: 20210151591Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.Type: ApplicationFiled: December 12, 2019Publication date: May 20, 2021Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Yu-Chi Wang, Tsung-Mu Yang, Yu-Ren Wang
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Publication number: 20210134957Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.Type: ApplicationFiled: December 10, 2019Publication date: May 6, 2021Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Publication number: 20210066487Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.Type: ApplicationFiled: September 18, 2019Publication date: March 4, 2021Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Patent number: 10546922Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.Type: GrantFiled: February 6, 2018Date of Patent: January 28, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
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Patent number: 10468502Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.Type: GrantFiled: January 22, 2019Date of Patent: November 5, 2019Assignee: United Microelectronics Corp.Inventors: Chun-Liang Kuo, Tsang-Hsuan Wang, Yu-Ming Hsu, Tsung-Mu Yang, Ching-I Li
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Publication number: 20190229202Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.Type: ApplicationFiled: January 22, 2019Publication date: July 25, 2019Applicant: United Microelectronics Corp.Inventors: Chun-Liang Kuo, Tsang-Hsuan Wang, Yu-Ming Hsu, Tsung-Mu Yang, Ching-I Li
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Patent number: 10263096Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.Type: GrantFiled: January 24, 2018Date of Patent: April 16, 2019Assignee: United Microelectronics Corp.Inventors: Chun-Liang Kuo, Tsang-Hsuan Wang, Yu-Ming Hsu, Tsung-Mu Yang, Ching-I Li
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Patent number: 10236179Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.Type: GrantFiled: April 14, 2016Date of Patent: March 19, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Cheng Yen, Tsung-Mu Yang, Sheng-Hsu Liu, Tsang-Hsuan Wang, Chun-Liang Kuo, Yu-Ming Hsu, Chung-Min Tsai, Yi-Wei Chen
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Publication number: 20180166532Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.Type: ApplicationFiled: February 6, 2018Publication date: June 14, 2018Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
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Publication number: 20180097110Abstract: A method for manufacturing a semiconductor structure comprises the following steps. First, a recess is formed in a substrate. At least one wet cleaning process is performed to the recess and the substrate. Then, a baking process is performed to the recess and the substrate in an atmosphere containing H2 gas. After the baking process, a dry cleaning process is performed the recess and the substrate.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Tsung-Mu Yang, Kuang-Hsiu Chen, Chun-Liang Kuo, Tsang-Hsuan Wang, Yu-Ming Hsu, Fu-Cheng Yen, Chung-Min Tsai
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Patent number: 9929234Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.Type: GrantFiled: May 3, 2016Date of Patent: March 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
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Publication number: 20170301536Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.Type: ApplicationFiled: April 14, 2016Publication date: October 19, 2017Inventors: Fu-Cheng Yen, Tsung-Mu Yang, Sheng-Hsu Liu, Tsang-Hsuan Wang, Chun-Liang Kuo, Yu-Ming Hsu, Chung-Min Tsai, Yi-Wei Chen
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Publication number: 20170294508Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.Type: ApplicationFiled: May 3, 2016Publication date: October 12, 2017Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
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Publication number: 20170133460Abstract: The present invention provides a method for forming a semiconductor structure, including: first, a substrate is provided. Next, at least two gate structures are formed on the substrate, each gate structure including two spacers disposed on two sides of the gate structure. Afterwards, a dry etching process is performed to remove parts of the substrate, so as to form a recess in the substrate, and a wet etching process is performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively. In addition, parts of the spacer are also removed through the wet etching process, and each spacer includes a rounding corner disposed on a bottom surface of the spacer.Type: ApplicationFiled: November 9, 2015Publication date: May 11, 2017Inventors: Tien-I Wu, I-cheng Hu, Yu-Shu Lin, Chun-Jen Chen, Tsung-Mu Yang, Kun-Hsin Chen, Neng-Hui Yang, Shu-Yen Chan
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Patent number: 9214551Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.Type: GrantFiled: February 19, 2014Date of Patent: December 15, 2015Assignee: United Microelectronics Corp.Inventors: Ming-Hua Chang, Tien-Wei Yu, I-Cheng Hu, Chieh-Lung Wu, Yu-Shu Lin, Chun-Jen Chen, Tsung-Mu Yang, Tien-Chen Chan, Chin-Cheng Chien
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Publication number: 20150236158Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Applicant: United Microelectronics Corp.Inventors: Ming-Hua Chang, Tien-Wei Yu, I-Cheng Hu, Chieh-Lung Wu, Yu-Shu Lin, Chun-Jen Chen, Tsung-Mu Yang, Tien-Chen Chan, Chin-Cheng Chien
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Publication number: 20150170916Abstract: A semiconductor process includes the steps of providing a substrate with fin structures formed thereon, performing an epitaxy process to grow an epitaxial structure on each fin structure, forming a conformal cap layer on each epitaxial structure, where adjacent conformal cap layers contact each other, and performing an etching process to separate contacting conformal cap layers.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tien-Wei Yu, Chun-Jen Chen, Tsung-Mu Yang, Ming-Hua Chang, Yu-Shu Lin, Chin-Cheng Chien