Patents by Inventor Tsung-Wen Chen
Tsung-Wen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250047835Abstract: Methods for video encoding, computing devices, and non-transitory computer readable storage mediums are provided. One method includes obtaining multiple blocks divided from a video picture, where each of the multiple blocks is to be encoded by an intra prediction mode or an inter prediction mode; for a current block in the multiple blocks: in response to the current block satisfying multiple pre-defined conditions, determining whether weighted prediction is enabled for the current block, and determining whether different weights are used when averaging list 0 predicted samples and list 1 predicted samples for the current block; determining whether to disable an application of Decoder-side Motion Vector Refinement (DMVR) on the current block based on at least one of the two determinations when DMVR is configured to be applied in a current picture that comprises the current block; and forming a bitstream based on prediction mode information of the current block.Type: ApplicationFiled: October 17, 2024Publication date: February 6, 2025Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.Inventors: Yi-Wen CHEN, Xiaoyu XIU, Xianglin WANG, Tsung-Chuan MA
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Patent number: 12219125Abstract: A method of constraining the operations of certain inter-mode coding tools in the derivation of motion vector candidates for inter-mode coded blocks employed in video coding standards, such as the now-current Versatile Video Coding (VVC), is performed at a computing device. The computing device determines whether one or more of the reference pictures associated with an inter-mode coded block involved in an operation of an inter-mode coding tool are long-term reference pictures, and constrains the operation of the inter-mode coding tool on the inter-mode coded block based on the determination.Type: GrantFiled: August 13, 2021Date of Patent: February 4, 2025Assignee: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.Inventors: Yi-Wen Chen, Xiaoyu Xiu, Xianglin Wang, Tsung-Chuan Ma
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Publication number: 20250039463Abstract: An electronic apparatus performs a method of decoding video data. The method comprises: receiving, from bitstream, a plurality of syntax elements associated with a coding unit, wherein the plurality of syntax elements indicate a size of the coding unit and a coding tree type of the coding unit; determining a minimum palette mode block size for the coding unit in accordance with the coding tree type of the coding unit; in accordance with a determination that the size of the coding unit is greater than the minimum palette mode block size: receiving, from the bitstream, a palette mode enable flag associated with the coding unit; and decoding, from the bitstream, the coding unit in accordance with the palette mode enable flag.Type: ApplicationFiled: October 15, 2024Publication date: January 30, 2025Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.Inventors: Hong-Jheng JHU, Yi-Wen Chen, Xiaoyu Xiu, Xianglin Wang, Tsung-Chuan Ma, Bing Yu
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Publication number: 20250027502Abstract: An axial-flow heat dissipation fan including a frame, a hub, and a plurality of blades is provided. The frame has an air inlet and an air outlet. The hub is rotatably arranged in the frame. The blades disposed at side of the hub respectively and rotate along with the hub. Each of the blades has a front surface facing toward the air inlet and a rear surface facing toward the air outlet. A surface roughness of the front surface is different from a surface roughness of the rear surface.Type: ApplicationFiled: July 8, 2024Publication date: January 23, 2025Applicant: Acer IncorporatedInventors: Cheng-Wen Hsieh, Mao-Neng Liao, Kuang-Hua Lin, Wei-Chin Chen, Tsung-Ting Chen
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Publication number: 20250028036Abstract: A positioning method and a multi-radar positioning system are provided. In the positioning method, a first object and a second object are detected by a first radar to obtain a first coordinate and a second coordinate on a first coordinate system respectively. The first object and the second object are detected by a second radar to obtain a third coordinate and a fourth coordinate on a second coordinate system respectively. A first candidate coordinate and a second candidate coordinate of the second radar on the first coordinate system are estimated according to the third coordinate and the fourth coordinate. The first candidate coordinate is selected from the first candidate coordinate and the second candidate coordinate as a first radar coordinate of the second radar according to the first coordinate and the second coordinate. The first radar coordinate is output.Type: ApplicationFiled: September 7, 2023Publication date: January 23, 2025Applicant: Wistron CorporationInventors: Yin-Yu Chen, Yu-Wen Huang, Kaijen Cheng, Tsung-Yin Tsou, Yao-Tsung Chang
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Publication number: 20250030872Abstract: Methods, apparatuses, and non-transitory computer-readable storage mediums are provided for decoding a video signal. A decoder partitions a video picture into a plurality of coding units (CUs) comprising a lossless CU. The decoder may further receive a high-level syntax. The high-level syntax may include, for example, a first flag that indicates whether a residual coding scheme is switchable.Type: ApplicationFiled: September 26, 2024Publication date: January 23, 2025Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.Inventors: Tsung-Chuan MA, Xianglin WANG, Xiaoyu XIU, Yi-Wen CHEN, Hong-Jheng JHU, Bing YU
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Publication number: 20250024084Abstract: A method for video coding is provided. The method includes: setting, by an encoder, a first syntax element in a picture parameter set (PPS) specifying whether a picture corresponding to the PPS comprises more than one network abstraction layer (NAL) units and whether the more than one NAL units have a same NAL unit type; setting, by the encoder, a second syntax element in a picture header (PH) specifying whether the picture corresponding to the PH is an intra random access point (IRAP) picture or a gradual decoding refresh (GDR) picture, where a value of the second syntax element is set based on a value of the first syntax element; and forming, by the encoder, a bitstream with the first syntax element and the second syntax element.Type: ApplicationFiled: July 19, 2024Publication date: January 16, 2025Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.Inventors: Xiaoyu XIU, Yi-wen CHEN, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Xianglin WANG, Bing YU
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Publication number: 20240395605Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
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Patent number: 12100617Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.Type: GrantFiled: April 13, 2023Date of Patent: September 24, 2024Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
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Patent number: 11881503Abstract: The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.Type: GrantFiled: December 9, 2022Date of Patent: January 23, 2024Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pei-Ting Tsai, Yu-Cheng Tung, Tsuo-Wen Lu, Min-Teng Chen, Tsung-Wen Chen
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Publication number: 20230255018Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.Type: ApplicationFiled: April 13, 2023Publication date: August 10, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
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Patent number: 11665885Abstract: A semiconductor memory device is provided in the present invention, including a substrate, word lines in the substrate, bit lines over the word lines, partition structures between the bit lines and right above the word lines, storage node contacts in spaces defined by the bit lines and the partition structures and electrically connecting with the substrate, wherein a portion of the storage node contact protruding from top surfaces of the bit lines and the partition structures is contact pad, and contact pad isolation structures on the partition structures and between the contact pads, wherein the contact pad isolation structure includes outer silicon nitride layers and inner silicon oxide layers.Type: GrantFiled: May 12, 2021Date of Patent: May 30, 2023Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
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Publication number: 20230106501Abstract: The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.Type: ApplicationFiled: December 9, 2022Publication date: April 6, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pei-Ting Tsai, Yu-Cheng Tung, Tsuo-Wen Lu, Min-Teng Chen, Tsung-Wen Chen
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Patent number: 11557645Abstract: The present invention provides a semiconductor memory device and a fabricating method thereof. The semiconductor memory device includes a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.Type: GrantFiled: April 16, 2021Date of Patent: January 17, 2023Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pei-Ting Tsai, Yu-Cheng Tung, Tsuo-Wen Lu, Min-Teng Chen, Tsung-Wen Chen
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Publication number: 20220208959Abstract: The present invention provides a semiconductor memory device and a fabricating method thereof. The semiconductor memory device includes a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.Type: ApplicationFiled: April 16, 2021Publication date: June 30, 2022Inventors: Pei-Ting Tsai, Yu-Cheng Tung, Tsuo-Wen Lu, Min-Teng Chen, Tsung-Wen Chen
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Publication number: 20210375878Abstract: A semiconductor memory device is provided in the present invention, including a substrate, word lines in the substrate, bit lines over the word lines, partition structures between the bit lines and right above the word lines, storage node contacts in spaces defined by the bit lines and the partition structures and electrically connecting with the substrate, wherein a portion of the storage node contact protruding from top surfaces of the bit lines and the partition structures is contact pad, and contact pad isolation structures on the partition structures and between the contact pads, wherein the contact pad isolation structure includes outer silicon nitride layers and inner silicon oxide layers.Type: ApplicationFiled: May 12, 2021Publication date: December 2, 2021Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
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Publication number: 20210341763Abstract: The present invention discloses a kind of anti-pollen glasses includes a glass frame and a protection cover, the protection cover is detachably assembled at an outer side of the glass frame and has an accommodation groove adapting to the glass frame, a side wall of the accommodation groove encloses the whole glass frame and forms a protection ring surface, the protection cover is provided with relief windows corresponding to positions of the lenses. The structure of the present invention is simple, a protection cover is added on the basis of regular glasses, and the glasses can be used as the regular glasses after the protection cover is removed. It is convenient for assembling and disassembling, in an environment where anti-pollen is not required, a wearer can easily detach the protection cover to reduce pressure on a face, and can conveniently assemble the protection cover when necessary.Type: ApplicationFiled: September 28, 2020Publication date: November 4, 2021Inventors: TSUNG-WEN CHEN, Xiaoxian HUANG
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Publication number: 20170227787Abstract: Provided is a connection structure between a frame and legs of a pair of eyeglasses. A pivoting end of a leg is formed as a rotating shaft; correspondingly a pivoting end of a frame is formed as a rotating shaft base; an upper clip, an intermediate clip, and a lower clip extend from the rotating shaft base of the frame; the intermediate clip is staggered with the upper clip and the lower clip, the rotating shaft of the leg is clamped between the intermediate clip, the upper clip and the lower clip, and the rotating shaft of the leg rotates between the intermediate clip, the upper clip and the lower clip, enabling the leg to fold closed and open. The connection between the frame and the leg is screw-less, providing a simple structure, convenient installation, and comfortable wear.Type: ApplicationFiled: October 29, 2014Publication date: August 10, 2017Inventor: Tsung-wen Chen
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Patent number: 9715128Abstract: Disclosed is a connecting structure for spectacle temples. An axle slot and axle hole are formed coaxially on a spectacle frame and a preemptive groove transversely on the spectacle frame, with the preemptive groove being linked up with the axle slot at a position thereof close to the axle hole; a pivot and connecting section are formed on a spectacle temple, the connecting section is in connection with the middle of the pivot, an elastic cutting slot is respectively formed on the two ends of the pivot, the two ends of the pivot are inserted in the axle hole and axle slot, and the connecting section is aligned with the preemptive groove, allowing the spectacle temple to be coupled pivotally to the spectacle frame. Whereby, the connection is secure, and the operation feel of closing and opening the spectacle is better.Type: GrantFiled: September 29, 2013Date of Patent: July 25, 2017Assignee: HWA MAO OPTICAL (XIAMEN) CO., LTD.Inventor: Tsung-Wen Chen
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Publication number: 20160223833Abstract: Disclosed is a connecting structure for spectacle temples. An axle slot and axle hole are formed coaxially on a spectacle frame and a preemptive groove transversely on the spectacle frame, with the preemptive groove being linked up with the axle slot at a position thereof close to the axle hole; a pivot and connecting section are formed on a spectacle temple, the connecting section is in connection with the middle of the pivot, an elastic cutting slot is respectively formed on the two ends of the pivot, the two ends of the pivot are inserted in the axle hole and axle slot, and the connecting section is aligned with the preemptive groove, allowing the spectacle temple to be coupled pivotally to the spectacle frame. Whereby, the connection is secure, and the operation feel of closing and opening the spectacle is better.Type: ApplicationFiled: September 29, 2013Publication date: August 4, 2016Applicant: HWA MAO Optical (XIAMEN) Co., Ltd.Inventor: Tsung-Wen Chen