Abstract: A physical vapor deposition (PVD) system is disclosed. The PVD system includes a pedestal configured to hold a semiconductor wafer, a cover plate configured to hold a target, and a collimator between the pedestal and the cover plate. The collimator includes a plurality of passages configured to pass source material travelling from the cover plate toward the pedestal at an angle less than a threshold angle with respect to a line perpendicular to a surface of the pedestal facing the cover plate, where the collimator is configured to block source material travelling from the cover plate toward the pedestal at an angle greater than the threshold angle, where a first passage of the plurality of passages has a first passage length, where a second passage of the plurality of passages has a second passage length, and where the first passage length is less than the second passage length.

Abstract: A physical vapor deposition (PVD) system is disclosed. The PVD system includes a pedestal configured to hold a semiconductor wafer, a cover plate configured to hold a target, and a collimator between the pedestal and the cover plate. The collimator includes a plurality of passages configured to pass source material travelling from the cover plate toward the pedestal at an angle less than a threshold angle with respect to a line perpendicular to a surface of the pedestal facing the cover plate, where the collimator is configured to block source material travelling from the cover plate toward the pedestal at an angle greater than the threshold angle, where a first passage of the plurality of passages has a first passage length, where a second passage of the plurality of passages has a second passage length, and where the first passage length is less than the second passage length.

Abstract: A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.

Abstract: A current amplifier and a transmitter using the same. The current amplifier includes: a first transistor having a gate coupled to a former-stage circuit, a drain coupled to a current source, and a source biased at a constant voltage level; a second transistor having a gate coupled to the current source and having a source and a drain; a first impedance circuit coupled between the gate of the first transistor and the source of the second transistor; and a second impedance circuit coupled between the source of the second transistor and a ground terminal. The current amplifier receives an input current from the former-stage circuit and generates an output current at the drain of the second transistor. Note that no current source is connected to the source of the first transistor.

Abstract: A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.

Abstract: A photosensitive composition and a photoresist are provided. The photoresist is formed by compounding a photosensitive composition. The photosensitive composition comprises a binder agent, a photomonomer and a photoinitiator. The binder agent has a chemical structure comprising following repeating unit: R1 is H or CH3, n is 2-40 of integer. The photomonomer has an amount of about 25-95 parts by weight relative to 100 parts by weight of a solid content of the binder agent. The photo initiator has an amount of about 0.5-15 parts by weight relative to 100 parts by weight of the solid content of the binder agent.

Abstract: A reading method of a memory is provided. The memory has a turn on window. The reading method comprises the following steps. A reading voltage is provided. The reading voltage is shown if the reading voltage is located in the turn on window. The reading voltage is updated by moving a predetermined distance if the reading voltage is not located in the turn on window. The predetermined distance is cut by half before the step of updating the reading voltage is performed again.

Abstract: A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying on the memory cell. The control unit determines a digital state of the first bit by comparing a first reference current with the first cell current or by comparing a reference data with a first delta current between the first cell current and the second cell current.

Abstract: The disclosure provides a white coating composition, and a device employing a coating made of the composition. The white coating composition includes 20-55 parts by weight of silicon dioxide particles, 40-75 parts by weight of inorganic material, and 5-40 parts by weight of silsequioxane, wherein the silsequioxane is prepared from monomers comprising a first monomer represented by the Formula (I) and a second monomer represented by the Formula (II) wherein, R1 is independently the same or different methyl or ethyl, and R2 is independently the same or different C1-6 alkyl.

Abstract: A current amplifier and a transmitter using the same. The current amplifier includes: a first transistor having a gate coupled to a former-stage circuit, a drain coupled to a current source, and a source biased at a constant voltage level; a second transistor having a gate coupled to the current source and having a source and a drain; a first impedance circuit coupled between the gate of the first transistor and the source of the second transistor; and a second impedance circuit coupled between the source of the second transistor and a ground terminal The current amplifier receives an input current from the former-stage circuit and generates an output current at the drain of the second transistor. Note that no current source is connected to the source of the first transistor.

Abstract: The disclosure provides a white coating composition, and a device employing a coating made of the composition. The white coating composition includes 20-55 parts by weight of silicon dioxide particles, 40-75 parts by weight of inorganic material, and 5-40 parts by weight of silsequioxane, wherein the silsequioxane is prepared from monomers comprising a first monomer represented by the Formula (I) and a second monomer represented by the Formula (II) wherein, R1 is independently the same or different methyl or ethyl, and R2 is independently the same or different C1-6 alkyl.

Abstract: A reading method of a memory is provided. The memory has a turn on window. The reading method comprises the following steps. A reading voltage is provided. The reading voltage is shown if the reading voltage is located in the turn on window. The reading voltage is updated by moving a predetermined distance if the reading voltage is not located in the turn on window. The predetermined distance is cut by half before the step of updating the reading voltage is performed again.

Abstract: A method of storing data in a multi-level charge-trapping memory array is described. An incidence-of-occurrence (i.e., frequency) analysis is performed on data to be programmed to identify data words combining a high programming voltage with a high frequency of occurrence. Those words are reassigned in order to reduce programming time.

Abstract: A method of efficiently programming charge-trapping memory cells includes sense amplifiers being dynamically connected to cells to be programmed, by switching bit lines. The method increases a number of cells that can be programmed simultaneously, such that an optimal use of sense amplifier resources is obtained.

Abstract: Methods are disclosed to compensate for a second-bit effect during programming and reading of charge-trapping memory cells having left and right data regions. When only one of the left and right data regions is to be programmed, a two-step programming procedure is performed on the data region to be programmed. When the memory cell is to be read, threshold voltages for the left and right data regions are sensed with a joint decision regarding left and right data bit values being reached depending upon both sensed threshold voltage values.

Abstract: A ground-plane slotted type signal transmission circuit board is proposed, which is designed for use with a high-speed digital signal processing system for providing a low-loss signal transmission function. The proposed circuit board structure is characterized by the formation of a slotted structure (i.e., elongated cutaway portion) in the ground plane at the beneath of each signal line. Since the slotted structure is a void portion, the electric field of a gigahertz signal being transmitting through the overlaying signal line would be unable to induce electric currents in the void portion of the ground plane. This feature allows the prevention of a leakage current that would otherwise flow from the signal line to the ground plane, and therefore can help prevent unnecessary power loss of the transmitted signal.

Abstract: A photosensitive composition and a photoresist are provided. The photoresist is formed by compounding a photosensitive composition. The photosensitive composition comprises a binder agent, a photomonomer and a photoinitiator. The binder agent is formed by polymerizing a binder composition. The binder composition comprises a lactic oligomer. The photomonomer has an amount of about 25-95 parts by weight relative to 100 parts by weight of a solid content of the binder agent. The photo initiator has an amount of about 0.5-15 parts by weight relative to 100 parts by weight of the solid content of the binder agent.

Abstract: The invention provides a method for reading a first data storage of a memory cell. The method comprises sensing a first current of the memory cell by applying a first bit line voltage on the memory cell. When the first current is larger than a first reference current with respect to the first bit line voltage, the first data storage is determined to be at an un-programmed state. Otherwise, a second current of the memory cell is sensed by applying a second bit line voltage on the memory cell. When the difference between the first current and the second current is larger than the difference between the first reference current and the second reference current, the first data storage is determined to be at the un-programmed state. Otherwise, the first data storage is determined to be at a programmed state.

Abstract: A method and apparatus are described that efficiently program charge-trapping memory cells by dynamically switching sense amplifiers and corresponding drivers depending upon data to be programmed. When a number of sense amplifier/drivers can be operated simultaneously, cells to be programmed to a same level are selected and programmed simultaneously employing up to the number of simultaneously operable sense amplifier/drivers.

Abstract: A method of storing data in a multi-level charge-trapping memory array is described. An incidence-of-occurrence (i.e., frequency) analysis is performed on data to be programmed to identify data words combining a high programming voltage with a high frequency of occurrence. Those words are reassigned in order to reduce programming time.