Patents by Inventor Tsung-Yi Lin

Tsung-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250000731
    Abstract: Disclosed in the present invention is a carrying module detachably provided on a host module. The carrying module comprises two mounting bases, two guardrails, two bearing plates, and a backrest assembly. The two guardrails are respectively connected and locked to the mounting bases by means of a first coupling device. The two bearing plates are respectively rotatably mounted at the bottoms of the two guardrails by a second coupling device. When being lifted upwards, the bearing plates are close to the guardrails, and when being horizontally placed, the bearing plates can be used for bearing weight. The backrest assembly is detachably connected and locked to the two guardrails by means of a third coupling device. The host module comprises a host body and a displacement module, which can be combined with a plurality of nursing modules to forma nursing machine, and can also be added with a push module to form a displacement machine.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 2, 2025
    Inventor: TSUNG-YI LIN
  • Patent number: 12176282
    Abstract: A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 12176465
    Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: December 24, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
  • Patent number: 12164158
    Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hsiang Hsu, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Chung-Ming Weng
  • Publication number: 20240398644
    Abstract: Disclosed are a main unit module and an assistive device equipped with the main unit module, for example, a nursing machine and an overhanging machine. The main unit module comprises a shifting module, a supporting framework module and a coupling module; the supporting framework module is assembled above the shifting module, the coupling module is provided on the supporting framework module. The opening and closing operations of wheel leg sets in the shifting module can drive and control the movement of the main unit module. The supporting framework module is loaded with a nursing module having different functions, so that the main unit module has a plurality of different nursing functions.
    Type: Application
    Filed: September 29, 2021
    Publication date: December 5, 2024
    Inventor: TSUNG-YI LIN
  • Patent number: 12159839
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Publication number: 20240395721
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 28, 2024
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Publication number: 20240395605
    Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
  • Publication number: 20240387368
    Abstract: A semiconductor device and method of manufacture are presented in which a first pad and a second pad are formed adjacent to each other. A first set of dummy pads is manufactured between the first pad and the second pad and bonding pads are formed in electrical connection to the first pad and the second pad.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chin-Yi Lin, Jie Chen, Sheng-Han Tsai, Yuan Sheng Chiu, Chou-Jui Hsu, Yu Kuei Yeh, Tsung-Shu Lin
  • Publication number: 20240378509
    Abstract: A computer-implemented method of generating scale-permuted models can generate models having improved accuracy and reduced evaluation computational requirements. The method can include defining, by a computing system including one or more computing devices, a search space including a plurality of candidate permutations of a plurality of candidate feature blocks, each of the plurality of candidate feature blocks having a respective scale. The method can include performing, by the computing system, a plurality of search iterations by a search algorithm to select a scale-permuted model from the search space, the scale-permuted model based at least in part on a candidate permutation of the plurality of candidate permutations.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Xianzhi Du, Yin Cui, Tsung-Yi Lin, Quoc V. Le, Pengchong Jin, Mingxing Tan, Golnaz Ghiasi, Xiaodan Song
  • Publication number: 20240379535
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
  • Patent number: 12142560
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
  • Publication number: 20240369759
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 12136262
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for performing instance segmentation by detecting and segmenting individual objects in an image. In one aspect, a method comprises: processing an image to generate data identifying a region of the image that depicts a particular object; obtaining data defining a plurality of example object segmentations; generating a respective weight value for each of the example object segmentations; for each of a plurality of pixels in the region of the image, determining a score characterizing a likelihood that the pixel is included in the particular object depicted in the region of the image using: (i) the example object segmentations, and (ii) the weight values for the example object segmentations; and generating a segmentation of the particular object depicted in the region of the image using the scores for the pixels in the region of the image.
    Type: Grant
    Filed: October 12, 2023
    Date of Patent: November 5, 2024
    Assignee: Google LLC
    Inventors: Weicheng Kuo, Anelia Angelova, Tsung-Yi Lin
  • Patent number: 12123571
    Abstract: A streetlight can allow for the installation of various network equipment through the design of a disassembling rack to meet the construction needs of a smart city. A network equipment management system provides the network leasing and the power supply leasing to enable the management of the network bandwidth, the network traffic, the network communication ports, or the network providing time, wherein the network is connected to network equipment, as well as the management of the power of the power supply, the power supply ports, or the power supply providing time, wherein the network is connected to the network equipment. Therefore, the streetlight and the network equipment management system in this application can be utilized in the construction of a smart city.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: October 22, 2024
    Assignee: Agileiots Investment Co., Ltd.
    Inventors: Jo-Yi Chiang, Chia-Chen Lin, Tsung-Hsun Kuo, Sheng Jung Wang
  • Patent number: 12105365
    Abstract: A light reflecting device includes two substrates and a liquid crystal layer. The two substrates are parallel to each other and respectively electrically connected to a voltage source to generate an electric field therebetween. Each of the two substrates has an inner surface having a horizontal orientation. The liquid crystal layer is formed by liquid crystal materials filled between the two substrates. The liquid crystal materials include liquid crystal molecules and ions of salt species. The liquid crystal molecules are at least formed by negative liquid crystals and chiral molecules. The liquid crystal layer is respectively switched to a diffuse reflection state and a specular reflection state by applying the electrical field generated by the voltage source in a first frequency and a second frequency. The second frequency is higher than the first frequency.
    Type: Grant
    Filed: February 15, 2024
    Date of Patent: October 1, 2024
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Tsung-Hsien Lin, Cheng-Chang Li, Li-Min Chang, Duan-Yi Guo, Kuan-Wu Lin
  • Patent number: 12105323
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 12100617
    Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: September 24, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
  • Publication number: 20240311959
    Abstract: A frame interpolation method generates an interpolated frame that is temporally between a first frame and a second frame. A first and a second interpolated frames are generated using motion vectors from a first motion estimator and a second motion estimator, respectively. A weighting map is generated based on indications from the first motion estimator. First pixel locations and second pixel locations in the weighting map are assigned weight values of 1 and 0, respectively. A weighted combination is calculated using the weighting map to produce the interpolated frame output, which includes the first pixel locations from the first interpolated frame and the second pixel locations from the second interpolated frame. The first and the second motion estimators may be an optical flow estimator and the game engine renderer, respectively. Alternatively, the first and the second motion estimators may be the game engine renderer and the optical flow estimator, respectively.
    Type: Application
    Filed: March 14, 2024
    Publication date: September 19, 2024
    Inventors: Tsung-Shian Huang, Huei-Long Wang, Yan-Hong Zhang, Chi-Chiang Huang, Kuo-Yi Wang, An-Li Wang, Chien-Nan Lin
  • Patent number: 12083284
    Abstract: A respiratory system includes a gas supply unit and a heating and humidifying unit. The gas supply unit includes a gas supply port; the heating and humidifying unit is detachably combined with the gas supply unit. The heating and humidifying unit includes a base, an adapter and a water tank. The base includes a control element, and the adapter is combined with the base and can rotate at least 90 degrees relative to the base. The water tank is detachably combined with the base, and the water tank includes a gas inlet and a gas outlet, wherein when the water tank is combined with the base, the gas inlet penetrates through an aperture of the base to be fluidly connected to the gas supply port, and the gas outlet is fluidly connected to the adapter.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 10, 2024
    Assignee: APEX MEDICAL CORP.
    Inventors: Chun-Yen Lin, Chung-Yi Lin, Jhih-Teng Yao, Chih-Tsan Chien, Tsung-Chung Kan, Hao-Yu Chan