Patents by Inventor Tsung-Yi Lin

Tsung-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240395605
    Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
  • Publication number: 20240395721
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 28, 2024
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Publication number: 20240387368
    Abstract: A semiconductor device and method of manufacture are presented in which a first pad and a second pad are formed adjacent to each other. A first set of dummy pads is manufactured between the first pad and the second pad and bonding pads are formed in electrical connection to the first pad and the second pad.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chin-Yi Lin, Jie Chen, Sheng-Han Tsai, Yuan Sheng Chiu, Chou-Jui Hsu, Yu Kuei Yeh, Tsung-Shu Lin
  • Publication number: 20240378509
    Abstract: A computer-implemented method of generating scale-permuted models can generate models having improved accuracy and reduced evaluation computational requirements. The method can include defining, by a computing system including one or more computing devices, a search space including a plurality of candidate permutations of a plurality of candidate feature blocks, each of the plurality of candidate feature blocks having a respective scale. The method can include performing, by the computing system, a plurality of search iterations by a search algorithm to select a scale-permuted model from the search space, the scale-permuted model based at least in part on a candidate permutation of the plurality of candidate permutations.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Xianzhi Du, Yin Cui, Tsung-Yi Lin, Quoc V. Le, Pengchong Jin, Mingxing Tan, Golnaz Ghiasi, Xiaodan Song
  • Publication number: 20240379535
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
  • Patent number: 12142560
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
  • Publication number: 20240369759
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 12136262
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for performing instance segmentation by detecting and segmenting individual objects in an image. In one aspect, a method comprises: processing an image to generate data identifying a region of the image that depicts a particular object; obtaining data defining a plurality of example object segmentations; generating a respective weight value for each of the example object segmentations; for each of a plurality of pixels in the region of the image, determining a score characterizing a likelihood that the pixel is included in the particular object depicted in the region of the image using: (i) the example object segmentations, and (ii) the weight values for the example object segmentations; and generating a segmentation of the particular object depicted in the region of the image using the scores for the pixels in the region of the image.
    Type: Grant
    Filed: October 12, 2023
    Date of Patent: November 5, 2024
    Assignee: Google LLC
    Inventors: Weicheng Kuo, Anelia Angelova, Tsung-Yi Lin
  • Patent number: 12123571
    Abstract: A streetlight can allow for the installation of various network equipment through the design of a disassembling rack to meet the construction needs of a smart city. A network equipment management system provides the network leasing and the power supply leasing to enable the management of the network bandwidth, the network traffic, the network communication ports, or the network providing time, wherein the network is connected to network equipment, as well as the management of the power of the power supply, the power supply ports, or the power supply providing time, wherein the network is connected to the network equipment. Therefore, the streetlight and the network equipment management system in this application can be utilized in the construction of a smart city.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: October 22, 2024
    Assignee: Agileiots Investment Co., Ltd.
    Inventors: Jo-Yi Chiang, Chia-Chen Lin, Tsung-Hsun Kuo, Sheng Jung Wang
  • Patent number: 12105365
    Abstract: A light reflecting device includes two substrates and a liquid crystal layer. The two substrates are parallel to each other and respectively electrically connected to a voltage source to generate an electric field therebetween. Each of the two substrates has an inner surface having a horizontal orientation. The liquid crystal layer is formed by liquid crystal materials filled between the two substrates. The liquid crystal materials include liquid crystal molecules and ions of salt species. The liquid crystal molecules are at least formed by negative liquid crystals and chiral molecules. The liquid crystal layer is respectively switched to a diffuse reflection state and a specular reflection state by applying the electrical field generated by the voltage source in a first frequency and a second frequency. The second frequency is higher than the first frequency.
    Type: Grant
    Filed: February 15, 2024
    Date of Patent: October 1, 2024
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Tsung-Hsien Lin, Cheng-Chang Li, Li-Min Chang, Duan-Yi Guo, Kuan-Wu Lin
  • Patent number: 12105323
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 12100617
    Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: September 24, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
  • Publication number: 20240311959
    Abstract: A frame interpolation method generates an interpolated frame that is temporally between a first frame and a second frame. A first and a second interpolated frames are generated using motion vectors from a first motion estimator and a second motion estimator, respectively. A weighting map is generated based on indications from the first motion estimator. First pixel locations and second pixel locations in the weighting map are assigned weight values of 1 and 0, respectively. A weighted combination is calculated using the weighting map to produce the interpolated frame output, which includes the first pixel locations from the first interpolated frame and the second pixel locations from the second interpolated frame. The first and the second motion estimators may be an optical flow estimator and the game engine renderer, respectively. Alternatively, the first and the second motion estimators may be the game engine renderer and the optical flow estimator, respectively.
    Type: Application
    Filed: March 14, 2024
    Publication date: September 19, 2024
    Inventors: Tsung-Shian Huang, Huei-Long Wang, Yan-Hong Zhang, Chi-Chiang Huang, Kuo-Yi Wang, An-Li Wang, Chien-Nan Lin
  • Patent number: 12083284
    Abstract: A respiratory system includes a gas supply unit and a heating and humidifying unit. The gas supply unit includes a gas supply port; the heating and humidifying unit is detachably combined with the gas supply unit. The heating and humidifying unit includes a base, an adapter and a water tank. The base includes a control element, and the adapter is combined with the base and can rotate at least 90 degrees relative to the base. The water tank is detachably combined with the base, and the water tank includes a gas inlet and a gas outlet, wherein when the water tank is combined with the base, the gas inlet penetrates through an aperture of the base to be fluidly connected to the gas supply port, and the gas outlet is fluidly connected to the adapter.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 10, 2024
    Assignee: APEX MEDICAL CORP.
    Inventors: Chun-Yen Lin, Chung-Yi Lin, Jhih-Teng Yao, Chih-Tsan Chien, Tsung-Chung Kan, Hao-Yu Chan
  • Patent number: 12079695
    Abstract: A computer-implemented method of generating scale-permuted models can generate models having improved accuracy and reduced evaluation computational requirements. The method can include defining, by a computing system including one or more computing devices, a search space including a plurality of candidate permutations of a plurality of candidate feature blocks, each of the plurality of candidate feature blocks having a respective scale. The method can include performing, by the computing system, a plurality of search iterations by a search algorithm to select a scale-permuted model from the search space, the scale-permuted model based at least in part on a candidate permutation of the plurality of candidate permutations.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: September 3, 2024
    Assignee: GOOGLE LLC
    Inventors: Xianzhi Du, Yin Cui, Tsung-Yi Lin, Quoc V. Le, Pengchong Jin, Mingxing Tan, Golnaz Ghiasi, Xiaodan Song
  • Patent number: 12080055
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training an image representation neural network.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: September 3, 2024
    Assignee: Google LLC
    Inventors: Tsung-Yi Lin, Barret Zoph, Ekin Dogus Cubuk, Golnaz Ghiasi, Quoc V. Le
  • Publication number: 20240282721
    Abstract: A package structure includes a first package. The first package has an active region and a peripheral region surrounding the active region. The first package includes a first redistribution structure, a second redistribution structure, a die, an encapsulant, and a seal ring structure. The second redistribution structure is disposed over the first redistribution structure. The die is disposed in the active region and is located between the first redistribution structure and the second redistribution structure. The encapsulant laterally encapsulates the die. The seal ring structure is disposed in the peripheral region. A first portion of the seal ring structure is embedded in the first redistribution structure, and a second portion of the seal ring structure is embedded in the second redistribution structure.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Tzuan-Horng Liu, Yen-Liang Lin
  • Publication number: 20240257510
    Abstract: An object localization network (OLN) can be used to localize object(s) (e.g., known and/or unknown object(s)) in an instance of vision data. Various implementations include detecting the localized object(s) based on the localization. Many implementations include processing the instance of vision data using the OLN to generate a objectness score (e.g., a centerness score) as well as an intersection of union (IoU) score for one or more proposed object locations in the instance of vision data. Object(s) can be localized in the instance of vision data based on the objectness scores and the IoU scores.
    Type: Application
    Filed: August 6, 2021
    Publication date: August 1, 2024
    Inventors: Weicheng Kuo, Tsung-Yi Lin, Anelia Angelova, Dahun Kim
  • Publication number: 20240241155
    Abstract: A probe card includes a structure stiffener unit including a base with a lower surface where central and peripheral supporting elements protrude out and a main circuit board is fixed, a space transformer and a probe head disposed thereunder, which are disposed to the supporting elements by bolts and defined with central and peripheral regions located correspondingly to the central and peripheral supporting elements respectively, and a metal supporting member fixed on the space transformer in a direct contact manner and located correspondingly to the central region. The supporting member has a lower surface coplanar with the lower end surface of the peripheral supporting element, which is abutted on the space transformer, and an upper surface against which the central supporting element is abutted. The space transformer has great structural strength, flatness and heat dissipation effect for satisfying the large-area requirement and great electrical property testing stability.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 18, 2024
    Applicant: MPI CORPORATION
    Inventors: CHIN-YI LIN, CHE-WEI LIN, HSUEH-CHIH WU, TSUNG-YI CHEN, SHANG-JUNG HSIEH, SHENG-YU LIN, CHIEN-KAI HUNG, SHENG-WEI LIN, SHU-JUI CHANG
  • Publication number: 20240211054
    Abstract: An electronic device includes a case and a shoulder button module. The shoulder button module is movably disposed in the case and includes a keycap, a push switch, and a touch sensing assembly. The keycap is exposed from the case. The push switch is located in the case and disposed under the keycap. When the keycap is pushed downward, the push switch is triggered. The touch sensing assembly is disposed in the keycap so as to sense an input command touched on the keycap.
    Type: Application
    Filed: October 12, 2023
    Publication date: June 27, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Tsung-Yi Lin, Chao-Yang Cheng, Shang-Yu Hung, Shiang-Cong Chen, Ying-Yu Chen, Wei-Ting Cheng, Jyun-Miao Hong