Abstract: A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

Abstract: A method and apparatus for a reinforced package are provided. A package component may be electrically coupled to a device through a plurality of electrical connections. A molding underfill may be interposed between the package component and the device and may encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The package component may also include a molding compound. The plurality of the electrical connections may extend through the molding compound with the molding underfill interposed between the molding compound and the device to encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The molding underfill may extend up one or more sides of the package component.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first functional region of an integrated circuit over a workpiece, and forming a second functional region of the integrated circuit over the workpiece. The method includes forming a guard ring around the first functional region of the integrated circuit. The guard ring is formed in a material layer disposed over the first functional region and the second functional region.

Abstract: A seal ring structure of an integrated circuit includes a seal ring and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a top electrode, a bottom electrode disposed below the top electrode, and a first insulating layer disposed between the top electrode and the bottom electrode. The MIM capacitor is disposed within the seal ring and the MIM capacitor is insulated from the seal ring.

Abstract: A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

Abstract: A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer.

Abstract: A method of making a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, the semiconductor substrate having a first region and a second region, wherein the first region is a conductive pad and the second region is adjacent to the first region. The method further includes forming a first protective layer overlying the passivation layer and forming an interconnect layer overlying the first protective layer. The method further includes forming a plurality of slots in the second region and forming a second protective layer overlying the interconnect layer, wherein the second protective layer fills each slot of the plurality of slots. The method further includes exposing a portion of the interconnect layer through the second protective layer; forming a barrier layer on the exposed portion of the interconnect layer; and forming a solder bump on the barrier layer.

Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.

Abstract: A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a wafer containing an interconnect structure. The interconnect structure includes a plurality of vias and interconnect lines. The semiconductor device includes a first conductive pad disposed over the interconnect structure. The first conductive pad is electrically coupled to the interconnect structure. The semiconductor device includes a plurality of second conductive pads disposed over the interconnect structure. The semiconductor device includes a passivation layer disposed over and at least partially sealing the first and second conductive pads. The semiconductor device includes a conductive terminal that is electrically coupled to the first conductive pad but is not electrically coupled to the second conductive pads.

Abstract: A semiconductor device includes a semiconductor die having first and second conductive pads, and a substrate having third and fourth bonding pads. A width ratio of the first conductive pad over the third bonding pad at an inner region is different from a width ratio of the second conductive pad over the fourth bonding pad at an outer region.

Abstract: An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.

Abstract: A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Abstract: Methods and apparatuses are disclosed for forming a post-passivation interconnect (PPI) guard ring over a circuit in a wafer forming a wafer level package (WLP). A circuit device comprises a guard ring and an active area. A passivation layer is formed on top of the circuit device over the guard ring and the active area, wherein the passivation layer contains a passivation contact connected to the guard ring. A first polymer layer is formed over the passivation layer. A PPI opening is formed within the first polymer layer or within the passivation layer over the passivation contact. A PPI guard ring is formed filling the PPI opening in touch with the passivation contact and extending on top of the first polymer layer or the passivation layer.

Abstract: A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

Abstract: In a method of improving ball strength of a semiconductor device, a ball pattern of a plurality of connection balls to be formed as electrical connections for the semiconductor device is received. The pattern includes a number of columns and rows crossing each other. The balls are arranged at intersections of the columns and rows. An arrangement of balls in a region of the ball pattern is modified so that the region includes no isolated balls.

Abstract: A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.

Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.

Abstract: Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a wafer containing an interconnect structure. The interconnect structure includes a plurality of vias and interconnect lines. The semiconductor device includes a first conductive pad disposed over the interconnect structure. The first conductive pad is electrically coupled to the interconnect structure. The semiconductor device includes a plurality of second conductive pads disposed over the interconnect structure. The semiconductor device includes a passivation layer disposed over and at least partially sealing the first and second conductive pads. The semiconductor device includes a conductive terminal that is electrically coupled to the first conductive pad but is not electrically coupled to the second conductive pads.