Patents by Inventor Tsung-Yuan Yu

Tsung-Yuan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Packaging devices and methods of manufacture thereof
    Patent number: 9355906
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Ming-Da Cheng, Wen-Hsiung Lu
  • Capacitor in post-passivation structures and methods of forming the same
    Patent number: 9355954
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Packaging devices and methods of manufacture thereof
    Patent number: 9355978
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
  • Methods and apparatus of packaging of semiconductor devices
    Patent number: 9349665
    Abstract: Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area. An UBM pad extends into and fills the first opening of the dielectric layer, above the first area between the first opening and the second opening, and may further extends down at least partly into the second opening covering a part or the whole of the second opening of the dielectric layer. The UBM pad may further extend over a part of the second area of the dielectric layer if the UBM pad fills the whole of the second opening of the dielectric layer. A solder ball may be mounted on the UBM pad.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Jie Chen, Ying-Ju Chen
  • Ball Amount Process in the Manufacturing of Integrated Circuit
    Publication number: 20160141261
    Abstract: An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.
    Type: Application
    Filed: January 25, 2016
    Publication date: May 19, 2016
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Wen-Hsiung Lu, Ming-Da Cheng
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF HAVING GUARD RING STRUCTURE
    Publication number: 20160133583
    Abstract: In some embodiments, an integrated circuit (IC) device includes a substrate having a first functional region, a second functional region and a third functional region. The IC device also includes a plurality of dielectric layers over the substrate, a first guard ring in the plurality of dielectric layers and around the first functional region, and a second guard ring in the plurality of dielectric layers and around the second functional region. The second guard ring is separate from the first guard ring, and the third functional region is free of a guard ring. The IC device further includes a seal ring in the plurality of dielectric layers. The seal ring encircles the first and the second guard rings, and is separate from the first and the second guard rings.
    Type: Application
    Filed: January 15, 2016
    Publication date: May 12, 2016
    Inventors: Hsien-Wei Chen, Nien-Fang Wu, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • System and Method for an Improved Interconnect Structure
    Publication number: 20160133482
    Abstract: Presented herein are an interconnect structure and method for forming the same. The interconnect structure comprises a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer comprising a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 ?m.
    Type: Application
    Filed: January 14, 2016
    Publication date: May 12, 2016
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu, Tsung-Yuan Yu
  • Chip package and method of manufacturing the same
    Patent number: 9337117
    Abstract: A package comprises a semiconductor device. The semiconductor device comprises an active surface and side surfaces. The active surface has a contact pad. The package also comprises a mold covering the side surfaces of the semiconductor device. The package further comprises an interconnection line coupled with the contact pad and extending over the active surface of the semiconductor device. The package additionally comprises an under-bump metallurgy (UBM) layer over the interconnection line. The package also comprises a seal ring structure extending around and outside an upper periphery of the semiconductor device on the mold, the seal ring structure comprising a seal layer extending on a same level as at least one of the interconnection line or the UBM layer.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: May 10, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ying Yang, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
  • Semiconductor device and method of manufacturing the same
    Patent number: 9337154
    Abstract: A semiconductor device includes a substrate comprising a front surface, side surfaces, a back surface, and a recessed edge between the side surfaces and either the front surface or the back surface, the front surface comprising an active region, the active region comprising at least one contact pad, a polymeric member disposed and contacted with the recessed edge of the substrate, a mold disposed over the front surface of the substrate and the polymeric member, and an interface between the mold and the polymeric member.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: May 10, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Miao, Yen-Ping Wang, Hao-Yi Tsai, Shih-Wei Liang, Tsung-Yuan Yu
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160126324
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Inventors: CHEN-HUA YU, MIRNG-JI LII, HUNG-YI KUO, HAO-YI TSAI, TSUNG-YUAN YU, MIN-CHIEN HSIAO, CHAO-WEN SHIH
  • Interconnect Structures and Methods of Forming Same
    Publication number: 20160118359
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
    Type: Application
    Filed: January 8, 2016
    Publication date: April 28, 2016
    Inventors: Wen-Hsiung Lu, Hsuan-Ting Kuo, Tsung-Yuan Yu, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160099223
    Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 7, 2016
    Inventors: CHEN-CHIH HSIEH, HAO-YI TSAI, CHAO-WEN SHIH, YUNG-PING CHIANG, TSUNG-YUAN YU
  • 3D package with through substrate vias
    Patent number: 9305877
    Abstract: A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hung-Yi Kuo, Hao-Yi Tsai, Chao-Wen Shih, Tsung-Yuan Yu, Min-Chien Hsiao
  • Apparatus for package reinforcement using molding underfill
    Patent number: 9287143
    Abstract: A method and apparatus for a reinforced package are provided. A package component may be electrically coupled to a device through a plurality of electrical connections. A molding underfill may be interposed between the package component and the device and may encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The package component may also include a molding compound. The plurality of the electrical connections may extend through the molding compound with the molding underfill interposed between the molding compound and the device to encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The molding underfill may extend up one or more sides of the package component.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Wen-Hsiung Lu, Ming-Da Cheng, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160064338
    Abstract: A semiconductor device includes a substrate comprising a front surface, side surfaces, a back surface, and a recessed edge between the side surfaces and either the front surface or the back surface, the front surface comprising an active region, the active region comprising at least one contact pad, a polymeric member disposed and contacted with the recessed edge of the substrate, a mold disposed over the front surface of the substrate and the polymeric member, and an interface between the mold and the polymeric member.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Inventors: CHIA-CHUN MIAO, YEN-PING WANG, HAO-YI TSAI, SHIH-WEI LIANG, TSUNG-YUAN YU
  • System and method for an improved interconnect structure
    Patent number: 9275925
    Abstract: Presented herein are an interconnect structure and method for forming the same. The interconnect structure comprises a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening and a mounting pad opening. A post passivation layer comprising a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad separated from the trace by a trace gap, which may optionally be at least 10 ?m.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu, Tsung-Yuan Yu
  • Ball amount process in the manufacturing of integrated circuit
    Patent number: 9269658
    Abstract: An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Wen-Hsiung Lu, Ming-Da Cheng
  • Method of forming bump structure
    Patent number: 9269682
    Abstract: A method of forming a bump structure includes forming a metallization layer on a top metal layer by electroless plating process, forming a polymer layer over the metallization layer; forming an opening on the polymer layer to expose the metallization layer, and forming a solder bump over the exposed metallization layer to make electrical contact with the top metal layer.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Ying-Ju Chen
  • Interconnect structures and methods of forming same
    Patent number: 9257333
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Hsuan-Ting Kuo, Tsung-Yuan Yu, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu
  • Semiconductor devices having guard ring structure and methods of manufacture thereof
    Patent number: 9245842
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first functional region of an integrated circuit over a workpiece, and forming a second functional region of the integrated circuit over the workpiece. The method includes forming a guard ring around the first functional region of the integrated circuit. The guard ring is formed in a material layer disposed over the first functional region and the second functional region.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Nien-Fang Wu, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu