Patents by Inventor Tsung-Yuan Yu

Tsung-Yuan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Inductor System and Method
    Publication number: 20160343794
    Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tsung-Yuan Yu
  • Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods
    Publication number: 20160329291
    Abstract: Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater.
    Type: Application
    Filed: July 22, 2016
    Publication date: November 10, 2016
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu
  • Capacitor in post-passivation structures and methods of forming the same
    Patent number: 9490203
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Packaging Devices and Methods of Manufacture Thereof
    Publication number: 20160276295
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Ming-Da Cheng, Wen-Hsiung Lu
  • Seal ring structure with metal-insulator-metal capacitor
    Patent number: 9449927
    Abstract: A seal ring structure of an integrated circuit includes a seal ring and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a top electrode, a bottom electrode disposed below the top electrode, and a first insulating layer disposed between the top electrode and the bottom electrode. The MIM capacitor is disposed within the seal ring and the MIM capacitor is insulated from the seal ring.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai, Hao-Yi Tsai, Tsung-Yuan Yu
  • Semiconductor device with post-passivation interconnect structure and method of forming the same
    Patent number: 9443812
    Abstract: A semiconductor device, including a protective layer overlying a contact pad and a dummy pad on a semiconductor substrate, an interconnect structure overlying the protective layer and contacting part of the dummy pad through a contact via passing through the protective layer, a bump overlying the interconnect structure positioned over the dummy pad.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
  • Semiconductor device and manufacturing method thereof
    Patent number: 9437490
    Abstract: A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Hung-Yi Kuo, Pi-Lan Chang
  • Finfet seal ring
    Patent number: 9437739
    Abstract: A semiconductor device includes a first front-end-of-line (FEOL) seal ring on a substrate, the seal ring comprising ring-shaped fin-like structures, integrated circuitry formed on the substrate, the integrated circuitry being circumscribed by the first seal ring, an isolation zone between the seal ring and the integrated circuitry, the isolation zone comprising a set of fin structures, each fin structure facing a same direction.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen
  • Semiconductor devices with ball strength improvement
    Patent number: 9437567
    Abstract: A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Ying-Ju Chen, Shih-Wei Liang
  • Packaging Devices and Methods of Manufacture Thereof
    Publication number: 20160254238
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.
    Type: Application
    Filed: May 11, 2016
    Publication date: September 1, 2016
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
  • Capacitor in Post-Passivation Structures and Methods of Forming the Same
    Publication number: 20160247757
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Inductor system and method
    Patent number: 9406739
    Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tsung-Yuan Yu
  • 3D Package With Through Substrate Vias
    Publication number: 20160218090
    Abstract: A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.
    Type: Application
    Filed: April 4, 2016
    Publication date: July 28, 2016
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hung-Yi Kuo, Hao-Yi Tsai, Chao-Wen Shih, Tsung-Yuan Yu, Min-Chien Hsiao
  • Packaging devices, methods of manufacture thereof, and packaging methods
    Patent number: 9401308
    Abstract: Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: July 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu
  • Semiconductor device having trench adjacent to receiving area and method of forming the same
    Patent number: 9397056
    Abstract: In some embodiments in accordance with the present disclosure, a semiconductor device including a semiconductor substrate is received. An interconnect structure is provided over the semiconductor substrate, and a passivation is provided over the interconnect structure. The passivation includes an opening such that a portion of the interconnect structure is exposed. Moreover, a dielectric is provided over the passivation, and a post-passivation interconnect (PPI) is provided over the dielectric. The PPI is configured to connect with the exposed portion of the interconnect structure through an opening in the dielectric. Furthermore, the PPI includes a receiving area for receiving a conductor, and a trench adjacent to the receiving area. In certain embodiments, the receiving area is defined by the trench.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: July 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Ping Wang, Chao-Wen Shih, Yung-Ping Chiang, Shih-Wei Liang, Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
  • Methods and apparatus for wafer level packaging
    Patent number: 9396973
    Abstract: A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Wen-Hsiung Lu, Hung-Jen Lin
  • Semiconductor device and manufacturing method thereof
    Patent number: 9379076
    Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: June 28, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Chih Hsieh, Hao-Yi Tsai, Chao-Wen Shih, Yung-Ping Chiang, Tsung-Yuan Yu
  • Semiconductor devices and methods of manufacture thereof having guard ring structure
    Patent number: 9379067
    Abstract: In some embodiments, an integrated circuit (IC) device includes a substrate having a first functional region, a second functional region and a third functional region. The IC device also includes a plurality of dielectric layers over the substrate, a first guard ring in the plurality of dielectric layers and around the first functional region, and a second guard ring in the plurality of dielectric layers and around the second functional region. The second guard ring is separate from the first guard ring, and the third functional region is free of a guard ring. The IC device further includes a seal ring in the plurality of dielectric layers. The seal ring encircles the first and the second guard rings, and is separate from the first and the second guard rings.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Nien-Fang Wu, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • Contact test structure and method
    Patent number: 9368417
    Abstract: A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Tsung-Yuan Yu, Ying-Ju Chen
  • Semiconductor package device and forming the same
    Patent number: 9362243
    Abstract: In some embodiments in accordance with the present disclosure, a semiconductor device having a semiconductor substrate is provided. A metal structure is disposed over the semiconductor substrate, and a post-passivation interconnect (PPI) is disposed over the metal structure. In addition, the upper surface of the PPI is configured to receive a bump thereon. In certain embodiments, the upper surface of the PPI for receiving the bump is substantially flat. A positioning member is formed over the PPI and configured to accommodate the bump. In some embodiments, the positioning member is configured to limit bump movement after the bump is disposed over the PPI so as to retain the bump at a predetermined position.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: June 7, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tsung-Yuan Yu