Patents by Inventor Tsuo-Wen Lu
Tsuo-Wen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9685533Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.Type: GrantFiled: February 21, 2016Date of Patent: June 20, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Fu-Yu Tsai
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Publication number: 20160329400Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.Type: ApplicationFiled: July 21, 2016Publication date: November 10, 2016Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
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Publication number: 20160276431Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.Type: ApplicationFiled: March 16, 2015Publication date: September 22, 2016Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
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Patent number: 9431483Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.Type: GrantFiled: March 16, 2015Date of Patent: August 30, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
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Patent number: 9349599Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.Type: GrantFiled: November 10, 2014Date of Patent: May 24, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Feng Ku, Shao-Wei Wang, Yi-Hui Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
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Publication number: 20160133474Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.Type: ApplicationFiled: November 10, 2014Publication date: May 12, 2016Inventors: Chih-Feng Ku, Shao-Wei Wang, Yi-Hui Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
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Patent number: 9330902Abstract: A method for forming a HfOx film based on atomic layer deposition (ALD) process includes: providing a substrate; dividing a plurality of ALD cycles as needed into multiple depositing stages, wherein each of the ALD cycles includes applying HfCl4 pulse and applying H2O pulse over the substrate and a content ratio of HfCl4 to H2O is different and increasing for the depositing stages; and performing the depositing stages to form a HfOx film.Type: GrantFiled: June 4, 2015Date of Patent: May 3, 2016Assignee: United Microelectronics Corp.Inventors: Tsai-Yu Wen, Shih-Cheng Chen, Shan Ye, Tsuo-Wen Lu, Yu-Ren Wang
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Patent number: 9130014Abstract: A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer.Type: GrantFiled: November 21, 2013Date of Patent: September 8, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Keng-Jen Lin, Yu-Ren Wang, Chien-Liang Lin, Tsuo-Wen Lu, Wei-Jen Chen, Chih-Chung Chen
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Patent number: 9117878Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.Type: GrantFiled: December 11, 2012Date of Patent: August 25, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Keng-Jen Lin, Yu-Ren Wang, Chih-Chung Chen, Tsuo-Wen Lu, Tsai-Yu Wen
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Publication number: 20150140780Abstract: A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Keng-Jen Lin, Yu-Ren Wang, Chien-Liang Lin, Tsuo-Wen Lu, Wei-Jen Chen, Chih-Chung Chen
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Patent number: 9034705Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.Type: GrantFiled: March 26, 2013Date of Patent: May 19, 2015Assignee: United Microelectronics Corp.Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
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Patent number: 8921238Abstract: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.Type: GrantFiled: September 19, 2011Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu, Chih-Chung Chen, Ying-Wei Yen
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Publication number: 20140295629Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.Type: ApplicationFiled: March 26, 2013Publication date: October 2, 2014Applicant: United Microelectronics Corp.Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
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Publication number: 20140199854Abstract: A method of forming a film is provided. The method includes at least the following steps. A first substrate and a second substrate are provided in a batch processing system, wherein a first surface of the first substrate is adjacent to a second surface of the second substrate, the first surface of the first substrate has a first surface condition, the second surface of the second substrate has a second surface condition, and the first surface condition is different from the second surface condition. A pretreatment gas is provided to the surfaces of the substrates for transforming the first surface condition and the second surface condition to a third surface condition. A reaction gas is provided to form the film on the surfaces, having the third surface condition, of the substrates.Type: ApplicationFiled: January 16, 2013Publication date: July 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Chung Chen, Tsuo-Wen Lu, Yu-Ren Wang
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Publication number: 20140162431Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Keng-Jen Lin, Yu-Ren Wang, Chih-Chung Chen, Tsuo-Wen Lu, Tsai-Yu Wen
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Patent number: 8697508Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. An oxide layer is formed and covers the gate structure and the substrate. A plasma process without oxygen is performed to densify the oxide layer. A material layer is formed and covers the oxide layer. The material layer and the oxide layer are etched to form a dual spacer.Type: GrantFiled: April 19, 2012Date of Patent: April 15, 2014Assignee: United Microelectronics Corp.Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
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Patent number: 8674452Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first gate structure disposed on the first region, wherein the first gate structure comprises a first high-k dielectric layer, a first work function metal layer, and a first metal layer disposed between the first high-k dielectric layer and the first work function metal layer; and a second gate structure disposed on the second region, wherein the second gate structure comprises a second high-k dielectric layer, a second work function metal layer, and a second metal layer disposed between the second high-k dielectric layer and the second work function metal layer, wherein the thickness of the second metal layer is lower than the thickness of the first metal layer.Type: GrantFiled: June 24, 2011Date of Patent: March 18, 2014Assignee: United Microelectronics Corp.Inventors: Chin-Cheng Chien, Tzung-Ying Lee, Tsuo-Wen Lu, Shu-Yen Chan, Jei-Ming Chen, Yu-Min Lin, Chun-Wei Hsu
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Publication number: 20140035070Abstract: A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k dielectric layer, and a work function layer disposed on and contacted with the barrier layer. The MOS transistor further includes a dielectric material spacer. The dielectric material spacer is disposed on the barrier layer of each of the first gate structure and the second gate structure and surrounding the work function layer of each of the first gate structure and the second gate structure.Type: ApplicationFiled: October 4, 2013Publication date: February 6, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Tsuo-Wen Lu, Tzung-Ying Lee, Jei-Ming Chen, Chun-Wei Hsu, Yu-Min Lin, Chia-Lung Chang, Chin-Cheng Chien, Shu-Yen Chan
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Patent number: 8580625Abstract: A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.Type: GrantFiled: July 22, 2011Date of Patent: November 12, 2013Inventors: Tsuo-Wen Lu, Tzung-Ying Lee, Jei-Ming Chen, Chun-Wei Hsu, Yu-Min Lin, Chia-Lung Chang, Chin-Cheng Chien, Shu-Yen Chan
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Publication number: 20130280878Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. An oxide layer is formed and covers the gate structure and the substrate. A plasma process without oxygen is performed to densify the oxide layer. A material layer is formed and covers the oxide layer. The material layer and the oxide layer are etched to form a dual spacer.Type: ApplicationFiled: April 19, 2012Publication date: October 24, 2013Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang