Patents by Inventor Tsutomu Hayakawa

Tsutomu Hayakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6948319
    Abstract: A cogeneration system is provided which includes a prime mover for obtaining power for driving a generator by combustion of a fuel, a waste heat boiler for recovering thermal energy from exhaust gas discharged from the prime mover, and a heat exchanger for heating air that is to be fed into an air conditioner by heat exchange with the exhaust gas discharged from the waste heat boiler. Drain water that is generated from the exhaust gas cooled by heat exchange in the air-heating heat exchanger (5) with the air that is to be fed into the air conditioner (30) is recovered by drain water recovery/supply means (36). The drain water recovery/supply means (36) supplies the drain water thus recovered to appliances (37, 38) that require comparatively high temperature water. Thermal energy can thus be recovered effectively from the drain water discharged from the heat exchanger on the downstream side of the waste heat boiler, thereby improving the efficiency of recovery of waste heat energy.
    Type: Grant
    Filed: January 21, 2002
    Date of Patent: September 27, 2005
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Tsutomu Hayakawa, Keiichi Samekawa, Yasuhiro Kume, Yuuji Mukano
  • Patent number: 6861319
    Abstract: There is provided a method of fabricating a gate electrode, including the steps of (a) forming a gate oxide film at a surface of a semiconductor substrate, (b) forming a multi-layered structure on the gate oxide film, the multi-layered structure including a polysilicon layer formed on the gate oxide film, a refractive metal silicide layer formed on the polysilicon layer, and a silicon nitride layer formed on the refractive metal silicide layer, (c) thermally annealing the multi-layered structure in a nitrogen atmosphere to thereby form a silicon nitride film on sidewalls of the polysilicon layer and the refractive metal silicide layer, and (d) oxidizing the semiconductor substrate and the multi-layered structure.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: March 1, 2005
    Assignee: Elpida Memory, Inc.
    Inventors: Akira Hoshino, Kanta Saino, Shinichi Horiba, Tsutomu Hayakawa
  • Publication number: 20040079088
    Abstract: A cogeneration system is provided which includes a prime mover for obtaining power for driving a generator by combustion of a fuel, a waste heat boiler for recovering thermal energy from exhaust gas discharged from the prime mover, and a heat exchanger for heating air that is to be fed into an air conditioner by heat exchange with the exhaust gas discharged from the waste heat boiler. Drain water that is generated from the exhaust gas cooled by heat exchange in the air-heating heat exchanger (5) with the air that is to be fed into the air conditioner (30) is recovered by drain water recovery/supply means (36). The drain water recovery/supply means (36) supplies the drain water thus recovered to appliances (37, 38) that require comparatively high temperature water. Thermal energy can thus be recovered effectively from the drain water discharged from the heat exchanger on the downstream side of the waste heat boiler, thereby improving the efficiency of recovery of waste heat energy.
    Type: Application
    Filed: December 24, 2003
    Publication date: April 29, 2004
    Inventors: Tsutomu Hayakawa, Keiichi Samekawa, Yasuhiro Kume, Yuuji Mukano
  • Patent number: 6723608
    Abstract: A method for manufacturing a DRAM includes the steps of forming a gate oxide film, a polysilicon film and a tungsten silicide film consecutively on a silicon substrate, selective etching the tungsten silicide film, covering exposed side surfaces of the tungsten silicide film by a polysilicon side-wall film, selectively etching the polysilicon film, oxidizing the polysilicon side-wall film and exposed surfaces of the polysilicon film, and forming a gate electrode including the polysilicon film and the tungsten silicide film. The resultant DRAM has lower leakage current and excellent refresh characteristics due to less contamination of diffused regions by the tungsten particles.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: April 20, 2004
    Assignee: Elpida Memory, Inc.
    Inventor: Tsutomu Hayakawa
  • Publication number: 20030190798
    Abstract: A method for manufacturing a DRAM includes the steps of forming a gate oxide film, a polysilicon film and a tungsten silicide film consecutively on a silicon substrate, selective etching the tungsten silicide film, covering exposed side surfaces of the tungsten silicide film by a polysilicon side-wall film, selectively etching the polysilicon film, oxidizing the polysilicon side-wall film and exposed surfaces of the polysilicon film, and forming a gate electrode including the polysilicon film and the tungsten silicide film. The resultant DRAM has lower leakage current and excellent refresh characteristics due to less contamination of diffused regions by the tungsten particles.
    Type: Application
    Filed: April 4, 2003
    Publication date: October 9, 2003
    Applicant: Elpida Memory, Inc.
    Inventor: Tsutomu Hayakawa
  • Publication number: 20030146457
    Abstract: There is provided a method of fabricating a gate electrode, including the steps of (a) forming a gate oxide film at a surface of a semiconductor substrate, (b) forming a multi-layered structure on the gate oxide film, the multi-layered structure including a polysilicon layer formed on the gate oxide film, a refractive metal silicide layer formed on the polysilicon layer, and a silicon nitride layer formed on the refractive metal silicide layer, (c) thermally annealing the multi-layered structure in a nitrogen atmosphere to thereby form a silicon nitride film on sidewalls of the polysilicon layer and the refractive metal silicide layer, and (d) oxidizing the semiconductor substrate and the multi-layered structure.
    Type: Application
    Filed: February 3, 2003
    Publication date: August 7, 2003
    Inventors: Akira Hoshino, Kanta Saino, Shinichi Horiba, Tsutomu Hayakawa
  • Patent number: 6278151
    Abstract: A semiconductor device of the present invention has a base step area based on the step of a stacked capacitor array and has wiring layers formed over the stacked capacitors. A wiring layer arranged at the far most end part of the base step area is formed to detour the step area and the other wiring layers are arranged on the base step area.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: August 21, 2001
    Assignee: NEC Corporation
    Inventor: Tsutomu Hayakawa
  • Patent number: 5902717
    Abstract: A method of fabricating a semiconductor device having a semiconductor substrate, a chip region and a scribe region, includes a step of forming a first hole in an insulating film on the chip region by using a step-and-repeat lithography system using a half-tone phase shift mask, and forming a conductive film on an entire surface of the semiconductor substrate. The conductive film is patterned such that the conductive film remains at least at a second hole and its peripheral portion, the second hole resulting in being formed at a four-fold exposure portion which is a portion where a plurality of shots have overlapped at the scribe region during the step of forming the first hole. Since the conductive film remains at the second hole and its peripheral portion, it is possible to prevent the formation of residue of the conductive film at sidewalls of the second hole when the conductive film is etched away from the scribe region.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: May 11, 1999
    Assignee: NEC Corporation
    Inventor: Tsutomu Hayakawa
  • Patent number: 5789789
    Abstract: A manufacturing method for a semiconductor device is disclosed for effecting improvement of voltage resistance between an N-well and N-type diffusion layer without adversely affecting circuit and transistor characteristics. At the time of forming an N-well, a side wall composed of nitride layer is formed on the oxide layer that is used as a mask in phosphorus implantation, and the N-well is formed using as a mask the oxide layer on which this side wall is provided. The side wall is then removed, boron is implanted, and a channel stopper is formed only between the N-well and N-type diffusion layer. A channel stopper between N-type diffusion layers is formed subsequently as a separate step. In this way, the concentration of the channel stopper between the N-well and N-type diffusion can be set to a concentration different from that of the channel stopper between N-type diffusion layers.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: August 4, 1998
    Assignee: NEC Corporation
    Inventor: Tsutomu Hayakawa
  • Patent number: 4728111
    Abstract: A sheet gasket comprising a swelling sheet, a non-swelling layer laminated on the swelling sheet, and an adhesive layer coated on the surface of the non-swelling layer. This gasket is adapted to be inserted between flanges having different coefficients of thermal expansion, with the adhesive layer adhered to one of the flanges and the exposed swelling sheet adjacent to the other flange.
    Type: Grant
    Filed: November 10, 1986
    Date of Patent: March 1, 1988
    Assignees: Toyota Jidosha Kabushiki Kaisha, Asahi Asbestos Co., Ltd.
    Inventors: Kazuya Yoshijima, Tsutomu Hayakawa