Abstract: Provided is a novel crystalline solid electrolyte which can be used as a dispersion medium when slurrying polar solvents such as NMP, acetone, and DMF, and for which a decrease in conductivity when the crystalline solid electrolyte is immersed in said solvents can be suppressed. Proposed is a crystalline solid electrolyte represented by Compositional Formula: LixSiyPzSaHaw (here, Ha includes one or two or more of Br, Cl, I, and F, and 2.4<(x?y)/(y+z)<3.3), in which the content of S is 55 to 73% by mass, the content of Si is 2 to 11% by mass, and the content of a Ha element is 0.02% by mass or more.

Abstract: Provided is a novel crystalline solid electrolyte which can be used as a dispersion medium when slurrying polar solvents such as NMP, acetone, and DMF, and for which a decrease in conductivity when the crystalline solid electrolyte is immersed in said solvents can be suppressed. Proposed is a crystalline solid electrolyte represented by Compositional Formula: LixSiyPzSaHaw (here, Ha includes one or two or more of Br, Cl, I, and F, and 2.4<(x?y)/(y+z)<3.3), in which the content of S is 55 to 73% by mass, the content of Si is 2 to 11% by mass, and the content of a Ha element is 0.02% by mass or more.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: A semiconductor memory device includes a main memory includes a nonvolatile memory, and a buffer which stores input/output data of the nonvolatile memory, a buffer unit of the main memory, the buffer unit includes a volatile memory, a self-test interface includes a data input/output pin, and a controller which controls the main memory and the buffer unit. The controller at least stores data in the buffer from the self-test interface via the data input/output pin.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: A differential transmission line structure comprises an insulating layer, a grounded conductive layer laminated to the insulating layer, and a differential transmission line formed in the insulating layer. A region in which the conductive layer is removed is formed in correspondence with a position of the differential transmission line.

Abstract: A memory macro includes a variable number of memory cell arrays and associated circuits, and peripheral circuit elements such as line drivers, power-source transistors, and power-source capacitors coupled to the associated circuits. Multiple peripheral circuit elements of one type are placed side by side in a certain direction, aligned in that direction with one or more memory cell arrays, and are coupled in parallel to the associated circuits of those memory cell arrays. The number of these peripheral circuit elements is selected according to the number of memory cell arrays aligned with them, so that electrical requirements can be met without unnecessary consumption of space or current.

Abstract: A printed circuit board built-in type planar balun which can be easily incorporated in a printed circuit board without increasing the number of layers and lowering the functions thereof is provided. A balanced signal transmission line 1 and an unbalanced signal transmission line 2 are formed on a same plane, with the sides being opposed to each other. Dielectric layers 3 are provided between these transmission lines, and between the transmission line and a ground potential layer 4 which is arranged substantially parallel to the lines 1 and 2 and spaced at a predetermined distance.

Abstract: A memory macro includes a variable number of memory cell arrays and associated circuits, and peripheral circuit elements such as line drivers, power-source transistors, and power-source capacitors coupled to the associated circuits. Multiple peripheral circuit elements of one type are placed side by side in a certain direction, aligned in that direction with one or more memory cell arrays, and are coupled in parallel to the associated circuits of those memory cell arrays. The number of these peripheral circuit elements is selected according to the number of memory cell arrays aligned with them, so that electrical requirements can be met without unnecessary consumption of space or current.

Abstract: A memory macro includes a variable number of memory cell arrays and associated circuits, and peripheral circuit elements such as line drivers, power-source transistors, and power-source capacitors coupled to the associated circuits. Multiple peripheral circuit elements of one type are placed side by side in a certain direction, aligned in that direction with one or more memory cell arrays, and are coupled in parallel to the associated circuits of those memory cell arrays. The number of these peripheral circuit elements is selected according to the number of memory cell arrays aligned with them, so that electrical requirements can be met without unnecessary consumption of space or current.

Abstract: A semiconductor memory device comprises memory banks each including a memory cell array and a control circuit for the memory cell array and an interface circuit shared by the plural memory banks. The semiconductor memory device is adapted for performing reading of data from the plural memory banks and rewriting of data to the memory banks. In an operation mode for performing the reading, processings A1 to A4 are performed. In an operation mode for performing the rewriting, processings B1 to B3 are performed.

Abstract: There is provided a semiconductor package that includes a metal plate, and a wiring substrate having an insulating substrate, signal wiring layer formed on one surface of the insulating substrate, and a ground plane formed integrally on other surface of the insulating substrate, whereby a surface of the ground plane side of the wiring substrate is adhered onto the metal plate. The signal wiring layer is constructed by a wiring line portion and a connection pad portion whose width is thicker than a width of the wiring line portion, and non-forming portion is provided in portion of the ground plane, which corresponds to the connection pad portion. In addition, a recess portion may be formed in portion of the metal plate, which correspond to the non-forming portion.

Abstract: A semiconductor memory device comprises memory banks each including a memory cell array and a control circuit for the memory cell array and an interface circuit shared by the plural memory banks. The semiconductor memory device is adapted for performing reading of data from the plural memory banks and rewriting of data to the memory banks. In an operation mode for performing the reading, processings A1 to A4 are performed. In an operation mode for performing the rewriting, processings B1 to B3 are performed.

Abstract: There is provided a semiconductor package that includes a metal plate, and a wiring substrate having an insulating substrate, signal wiring layer formed on one surface of the insulating substrate, and a ground plane formed integrally on other surface of the insulating substrate, whereby a surface of the ground plane side of the wiring substrate is adhered onto the metal plate. The signal wiring layer is constructed by a wiring line portion and a connection pad portion whose width is thicker than a width of the wiring line portion, and non-forming portion is provided in portion of the ground plane, which corresponds to the connection pad portion. In addition, a recess portion may be formed in portion of the metal plate, which correspond to the non-forming portion.

Abstract: A memory macro includes a variable number of memory cell arrays and associated circuits, and peripheral circuit elements such as line drivers, power-source transistors, and power-source capacitors coupled to the associated circuits. Multiple peripheral circuit elements of one type are placed side by side in a certain direction, aligned in that direction with one or more memory cell arrays, and are coupled in parallel to the associated circuits of those memory cell arrays. The number of these peripheral circuit elements is selected according to the number of memory cell arrays aligned with them, so that electrical requirements can be met without unnecessary consumption of space or current.

Abstract: A memory macro includes a variable number of memory cell arrays and associated circuits, and peripheral circuit elements such as line drivers, power-source transistors, and power-source capacitors coupled to the associated circuits. Multiple peripheral circuit elements of one type are placed side by side in a certain direction, aligned in that direction with one or more memory cell arrays, and are coupled in parallel to the associated-circuits of those memory cell arrays. The number of these peripheral circuit elements is selected according to the number of memory cell arrays aligned with them, so that electrical requirements can be met without unnecessary consumption of space or current.

Abstract: A semiconductor device with an antenna including one or more antenna units for sending and receiving signals and a semiconductor element electrically connected to the antenna units, wherein the antenna units are formed by pressing or etching a thin metal sheet with substantially the same flat surface size as the semiconductor element, and the antenna units are integrally coupled to the surface of the semicondcutor element. The antenna units are formed in a plurality of layers separated by insulating layers, and the antenna units formed on the respective layers are connected electrically in series with each other.

Abstract: A composite material for use in making printed wiring boards comprising a carrier having releasable conductive fine particles on its surface. The composite is laminated to a substrate with the conductive fine particles facing the substrate and the carrier removed, leaving the surface of the conductive fine particles exposed. Printed wiring is formed using the conductive fine particles as its base, thus providing improved peel strength and permitting formation of fine wiring lines and spaces.