Abstract: A semiconductor operational circuit conducts real-time analog vector operations to permit the determination of the center of gravity of an image of a moving object. The circuit employs a first processing stage utilizing CMOS source follower circuits to perform weighted linear sum operations on the analog signals. A second processing stage utilizes comparator circuitry to perform comparison operations involving data from the weighted-sum and non-weighted-sum operations. A third processing stage utilizes exclusive OR gates to provide digital data outputs based on the comparison operation results.

Abstract: A photo-processing apparatus comprising at least a developing part for developing a photographic paper to which an image recorded on a developed photographic film is printed and a drying part for drying the developed photographic paper by the developing part. The apparatus includes a guide width synchronizing mechanism for synchronizing the width movement of a pair of guides being located between a guide width changing mechanism installed to a rack part for guiding the photographic paper in the developing part and the drying part, respectively, so as to adjust the spacing of a pair of the guides for guiding both side edges of the photographic paper. There can be provided an apparatus for processing photosensitive material which can precisely set the guide width of the rack for guiding conveyance of the photographic paper and which is easy to maintain and at the same time is inexpensive.

Abstract: A phase shift circuit suitable for use in an FM detecting circuit of quadrature detection method adopted for a FM radio receiver, for example. The phase shift circuit includes first and second pairs of differential transistors to which input signals are applied as differential inputs in common, first and second current sources for driving the first and second pairs of differential transistors, respectively, a first load circuit connected to respective collectors of the first pair of differential transistors, a second load circuit connected to an output side collector of the second pair of differential transistors and a third pair of differential transistors to which a first signal and a second signal are applied as differential inputs, wherein the first signal is derived from one of the collectors of the first pair of differential transistors, whereas the second signal is derived from the output side collector of the second pair of differential transistors.