Patents by Inventor Tsutomu Nakajima
Tsutomu Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8164610Abstract: A surface-condition-information obtaining unit obtains information on a surface condition of a rewritable display medium on which information is reversely displayed visually. A write-laser output unit outputs a write laser to irradiate the rewritable display medium with the write laser, to perform a drawing on the rewritable display medium. A control unit performs a write process for displaying an image on the rewritable display medium by adjusting a laser output condition based on the information obtained by the surface-condition-information obtaining unit and controlling the write-laser output unit based on an adjustment of the laser output condition.Type: GrantFiled: February 8, 2008Date of Patent: April 24, 2012Assignee: Ricoh Company, Ltd.Inventors: Yoshiko Nakata, Tsutomu Nakajima, Noriyuki Ochiai, Yukiko Sahashi, Yoshihiko Hotta, Shinya Kawahara, Hiroshi Uenishi, Tomomi Ishimi
-
Patent number: 8101683Abstract: An addition-curable silicone emulsion that exhibits stable curability even with a small amount of platinum. The curable emulsion composition is composed of an emulsion A and an emulsion B described below which are mixed together at the time of use, wherein the ratio of [number-average particle size of dispersed particles in emulsion A]/[number-average particle size of dispersed particles in emulsion B] is within a range from 0.4 to 2.0. The emulsion A comprises a specific alkenyl group-containing organopolysiloxane, a specific organohydrogenpolysiloxane, a nonionic surfactant, a polyvinyl alcohol and water, wherein the number-average particle size of the dispersed particles is within a range from 300 to 1,000 nm. The emulsion B comprises a specific alkenyl group-containing organopolysiloxane, a platinum-based complex, a nonionic surfactant, a polyvinyl alcohol and water, wherein the number-average particle size of the dispersed particles is within a range from 300 to 1,000 nm.Type: GrantFiled: May 28, 2010Date of Patent: January 24, 2012Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Shinji Irifune, Tsutomu Nakajima, Kenji Yamamoto
-
Publication number: 20110141325Abstract: An image pickup device without a light shielding device for blocking light received by a solid-state image pickup element, the image pickup device including: a supplying section configured to supply a signal for resetting a charge of a floating diffusion disposed so as to correspond to one or a plurality of pixels in the solid-state image pickup element; and a detecting section configured to detect a pixel in which change in output of the pixel after passage of a certain time from the resetting of the charge of the floating diffusion is larger than a predetermined threshold value.Type: ApplicationFiled: November 30, 2010Publication date: June 16, 2011Applicant: Sony CorporationInventor: Tsutomu Nakajima
-
Publication number: 20100305258Abstract: An addition-curable silicone emulsion that exhibits stable curability even with a small amount of platinum. The curable emulsion composition is composed of an emulsion A and an emulsion B described below which are mixed together at the time of use, wherein the ratio of [number-average particle size of dispersed particles in emulsion A]/[number-average particle size of dispersed particles in emulsion B] is within a range from 0.4 to 2.0. The emulsion A comprises a specific alkenyl group-containing organopolysiloxane, a specific organohydrogenpolysiloxane, a nonionic surfactant, a polyvinyl alcohol and water, wherein the number-average particle size of the dispersed particles is within a range from 300 to 1,000 nm. The emulsion B comprises a specific alkenyl group-containing organopolysiloxane, a platinum-based complex, a nonionic surfactant, a polyvinyl alcohol and water, wherein the number-average particle size of the dispersed particles is within a range from 300 to 1,000 nm.Type: ApplicationFiled: May 28, 2010Publication date: December 2, 2010Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Shinji Irifune, Tsutomu Nakajima, Kenji Yamamoto
-
Patent number: 7733487Abstract: A particle counting method is provided whereby a liquid sample is radiated by a laser light, scattered light produced by causing the laser light to hit a particle in the liquid sample is detected by a photoelectric conversion element, and a sample value which is the output of the photoelectric conversion element is sequentially compared to a threshold preset for each particle size range, thereby counting the number of particles for each particle size range, the method comprising: a timer start-up step for starting a timer of a predetermined time when the sample value becomes smaller than a threshold of a minimum particle size for the first time and for sequentially holding the maximum value of the sample value; and a timer extension step for restarting the timer to sequentially hold the maximum value of the sample value when the sample value at the time-out of the timer start-up step is larger than the threshold of the minimum particle size.Type: GrantFiled: April 4, 2008Date of Patent: June 8, 2010Assignee: Rion Co., Ltd.Inventor: Tsutomu Nakajima
-
Patent number: 7697334Abstract: Disclosed herein is a nonvolatile semiconductor memory device including: a first selection transistor configured to be connected to a bit line; a second selection transistor configured to be connected to a common source line; a memory cell configured to be connected in series between the first and second selection transistors; and writing means for carrying out writing for a selected memory cell. In the nonvolatile semiconductor memory device, the writing means applies a potential yielding a writing-blocked state via a bit line to a memory cell for which writing is not to be carried out, of a memory cell selected for writing, and the writing means carries out writing for a writing-target memory cell in a state in which a bit line has a bit line potential state dependent upon a threshold value state of the writing-target memory cell.Type: GrantFiled: August 27, 2007Date of Patent: April 13, 2010Assignee: Sony CorporationInventors: Tsutomu Nakajima, Kenji Kozakai, Koji Sakui
-
Patent number: 7542355Abstract: Disclosed herein is a semiconductor storage device including: a memory core having memory cells to be accessed; and an interface circuit having terminals operable to input and output a chip enable signal adapted to select a chip, at least one control signal adapted to control the chip operation, a clock signal adapted to control the chip I/O operation timing and a series of data including a command, address and data; wherein the interface circuit includes at least one input holding unit adapted to hold the control signal, and the interface circuit processes the control signal after loading it temporarily into the first input holding unit.Type: GrantFiled: September 25, 2007Date of Patent: June 2, 2009Assignee: Sony CorporationInventors: Kenji Kozakai, Tsutomu Nakajima, Koji Sakui
-
Patent number: 7515450Abstract: A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.Type: GrantFiled: May 21, 2007Date of Patent: April 7, 2009Assignee: Renesas Technology Corp.Inventors: Tsutomu Nakajima, Keiichi Yoshida
-
Publication number: 20090011254Abstract: Provided is a release film, including a plastic film substrate, a surface modification layer formed on a single surface or both surfaces of the plastic film substrate by radiating a flame of a fuel gas including an organosilicon compound onto the single surface or both surfaces, and a silicone release layer composed of a cured product of a curable silicone composition, in which the silicone release layer is provided on top of the surface modification layer. The release film exhibits excellent adhesion between the silicone release layer and the plastic film substrate.Type: ApplicationFiled: July 3, 2008Publication date: January 8, 2009Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Kenji Yamamoto, Tsutomu Nakajima, Masahiko Ogawa
-
Patent number: 7459213Abstract: A composition comprising the following components: 100 parts by weight of an organopolysiloxane (A), 0.1 to 30 parts by weight of a crosslinking agent (B), 50 to 1,000 parts by weight of a polyvinyl alcohol homopolymer or copolymer (C), 0 to 5 parts by weight, as an active ingredient, of a catalyst (D), 100 to 100,000 parts by weight of water (E), and 0.Type: GrantFiled: January 23, 2004Date of Patent: December 2, 2008Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Kenji Yamamoto, Masahiko Ogawa, Tsutomu Nakajima
-
Publication number: 20080246963Abstract: A particle counting method is provided whereby a liquid sample is radiated by a laser light, scattered light produced by causing the laser light to hit a particle in the liquid sample is detected by a photoelectric conversion element, and a sample value which is the output of the photoelectric conversion element is sequentially compared to a threshold preset for each particle size range, thereby counting the number of particles for each particle size range, the method comprising: a timer start-up step for starting a timer of a predetermined time when the sample value becomes smaller than a threshold of a minimum particle size for the first time and for sequentially holding the maximum value of the sample value; and a timer extension step for restarting the timer to sequentially hold the maximum value of the sample value when the sample value at the time-out of the timer start-up step is larger than the threshold of the minimum particle size.Type: ApplicationFiled: April 4, 2008Publication date: October 9, 2008Applicant: RION CO., LTD.Inventor: Tsutomu Nakajima
-
Publication number: 20080192618Abstract: A surface-condition-information obtaining unit obtains information on a surface condition of a rewritable display medium on which information is reversely displayed visually. A write-laser output unit outputs a write laser to irradiate the rewritable display medium with the write laser, to perform a drawing on the rewritable display medium. A control unit performs a write process for displaying an image on the rewritable display medium by adjusting a laser output condition based on the information obtained by the surface-condition-information obtaining unit and controlling the write-laser output unit based on an adjustment of the laser output condition.Type: ApplicationFiled: February 8, 2008Publication date: August 14, 2008Inventors: Yoshiko NAKATA, Tsutomu Nakajima, Noriyuki Ochiai, Yukiko Sahashi, Yoshihiko Hotta, Shinya Kawahara, Hiroshi Uenishi, Tomomi Ishimi
-
Publication number: 20080084742Abstract: Disclosed herein is a semiconductor storage device including: a memory core having memory cells to be accessed; and an interface circuit having terminals operable to input and output a chip enable signal adapted to select a chip, at least one control signal adapted to control the chip operation, a clock signal adapted to control the chip I/O operation timing and a series of data including a command, address and data; wherein the interface circuit includes at least one input holding unit adapted to hold the control signal, and the interface circuit processes the control signal after loading it temporarily into the first input holding unit.Type: ApplicationFiled: September 25, 2007Publication date: April 10, 2008Applicant: Sony CorporationInventors: Kenji Kozakai, Tsutomu Nakajima, Koji Sakui
-
Publication number: 20080064814Abstract: Composition comprising: 100 parts by weight of an organopolysiloxane (A), 0.1 to 30 parts by weight of a crosslinking agent (B), 50 to 1,000 parts by weight of a polyvinyl alcohol homopolymer or copolymer(C), 0 to 5 parts by weight, as an active ingredient, of a catalyst (D), 100 to 100,000 parts by weight of water (E), and. 0.1 to 100 parts by weight of a surfactant (F), wherein component (A) is an organopolysiloxane (A3) having at least two alkenyl groups and represented by the following formula (3): wherein each R1 may be same or different and is a group having 1 to 20 carbon atoms selected from the group consisting of alkyl groups, alicyclic groups, and aryl groups, whose hydrogen atoms bonded to the carbon atoms may partly be replaced with a halogen atom or a cyano group, R2 is an alkenyl group and X3is the group represented by the following formula: wherein a3, b3, c3, d3 and e3 are such numbers that the organopolysiloxane (A3) has a viscosity at 25 degrees C. of from 0.Type: ApplicationFiled: October 29, 2007Publication date: March 13, 2008Inventors: Kenji Yamamoto, Masahiko Ogawa, Tsutomu Nakajima
-
Publication number: 20080055999Abstract: Disclosed herein is a nonvolatile semiconductor memory device including: a first selection transistor configured to be connected to a bit line; a second selection transistor configured to be connected to a common source line; a memory cell configured to be connected in series between the first and second selection transistors; and writing means for carrying out writing for a selected memory cell. In the nonvolatile semiconductor memory device, the writing means applies a potential yielding a writing-blocked state via a bit line to a memory cell for which writing is not to be carried out, of a memory cell selected for writing, and the writing means carries out writing for a writing-target memory cell in a state in which a bit line has a bit line potential state dependent upon a threshold value state of the writing-target memory cell.Type: ApplicationFiled: August 27, 2007Publication date: March 6, 2008Applicant: Sony CorporationInventors: Tsutomu Nakajima, Kenji Kozakai, Koji Sakui
-
Publication number: 20080004815Abstract: A particle counter for measuring the number of floating particles contained in a sample to determine the particle concentration therein comprises: a memory section 11 for storing a discrete value C per unit of time based on the maximum particle number concentration set in the specification in advance; an operation processing section 12 for comparing a discrete value M per unit of time to be actually counted to the discrete value C per unit of time stored in the memory section 11; and an output section 4 for outputting the information based on the comparison results of the operation processing section 12.Type: ApplicationFiled: July 13, 2007Publication date: January 3, 2008Applicant: RION CO., LTD.Inventors: AKINORI TAKEDA, TSUTOMU NAKAJIMA, YASUTAKA NAKAJIMA, YUKIHIRO KIMOTO
-
Publication number: 20080002480Abstract: A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.Type: ApplicationFiled: September 6, 2007Publication date: January 3, 2008Inventors: Tsutomu Nakajima, Satoshi Noda, Kenji Kozakai, Atsushi Tokairin
-
Patent number: 7283408Abstract: A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.Type: GrantFiled: June 23, 2005Date of Patent: October 16, 2007Assignee: Renesas Technology Corp.Inventors: Tsutomu Nakajima, Satoshi Noda, Kenji Kozakai, Atsushi Tokairin
-
Publication number: 20070223275Abstract: A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.Type: ApplicationFiled: May 21, 2007Publication date: September 27, 2007Inventors: Tsutomu Nakajima, Keiichi Yoshida
-
Patent number: 7233523Abstract: A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.Type: GrantFiled: February 28, 2002Date of Patent: June 19, 2007Assignee: Renesas Technology Corp.Inventors: Tsutomu Nakajima, Keiichi Yoshida