Patents by Inventor Tsutomu Okazaki
Tsutomu Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130113494Abstract: The present invention relates to a chuck mechanism of a charge-discharge test device for a thin secondary battery, and aims to provide a chuck mechanism having excellent action controllability. The chuck mechanism includes: a chuck drive part which is movable in a direction toward a battery container housing a thin secondary battery; and a chuck activation part which is located away from the chuck drive part in the direction toward the battery container and whose movement in the same direction is restricted. In the chuck mechanism, when the chuck unit is moved in the direction toward the battery container, the chuck drive part activates a chuck member of the chuck activation part whose movement in the same direction is restricted.Type: ApplicationFiled: June 20, 2011Publication date: May 9, 2013Inventors: Takashi Nishihara, Takahiro Kawasaki, Tsutomu Okazaki, Takeshi Yasooka, Yoshikazu Niwa
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Patent number: 8390048Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: GrantFiled: October 14, 2010Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Takeshi Sakai, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Patent number: 8357968Abstract: A non-volatile memory semiconductor device having one end of an electricity supply line ESL arranged over a terminal end TE1 and the other end thereof arranged over a terminal end TE2, the central portion of the electricity supply line ESL being arranged over a dummy part DMY. The terminal end TE1, the terminal end TE2, and the dummy part DMY have substantially the same height, so that most of the electricity supply line ESL arranged from over the terminal end TE1 to over the terminal end TE2 via the dummy part DMY has the same height.Type: GrantFiled: September 12, 2009Date of Patent: January 22, 2013Assignee: Renesas Electronics CorporationInventors: Hiraku Chakihara, Tsutomu Okazaki
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Patent number: 8319265Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: October 16, 2009Date of Patent: November 27, 2012Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20110309837Abstract: The present invention relates to a chuck mechanism of a charge/discharge testing device for flat-rechargeable batteries and has a proposition to provide a chuck mechanism that makes it possible to lighten conventionally needed troublesome works, that is, for example, works of storing and fixing a large number of flat-rechargeable batteries in a container, and that is capable of surely chucking the flat-rechargeable batteries (electrodes). The chuck mechanism includes a first guide couplable with a battery storage retaining a plurality of flat-rechargeable batteries arranged in parallel, and a plurality of chuck units continuously joined with the first guide and resiliently arranged in parallel, wherein the chuck units each have a second guide resiliently positioning each of the chuck units with a predetermined number of corresponding flat-rechargeable batteries in the battery storage.Type: ApplicationFiled: June 16, 2011Publication date: December 22, 2011Inventors: Takashi NISHIHARA, Takahiro Kawasaki, Tsutomu Okazaki, Takeshi Yasooka, Hiroaki Habe, Yoshikazu Niwa
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Publication number: 20110175231Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tsutomu OKAZAKI, Motoi ASHIDA, Hiroji OZAKI, Tsuyoshi KOGA, Daisuke OKADA
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Patent number: 7939448Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.Type: GrantFiled: September 23, 2010Date of Patent: May 10, 2011Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Motoi Ashida, Hiroji Ozaki, Tsuyoshi Koga, Daisuke Okada
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Publication number: 20110024820Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: ApplicationFiled: October 14, 2010Publication date: February 3, 2011Inventors: Takeshi SAKAI, Yasushi ISHII, Tsutomu OKAZAKI, Masaru NAKAMICHI, Toshikazu MATSUI, Kyoya NITTA, Satoru MACHIDA, Munekatsu NAKAGAWA, Yuichi TSUKADA
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Publication number: 20110014783Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.Type: ApplicationFiled: September 23, 2010Publication date: January 20, 2011Applicant: Renesas Electronics CorporationInventors: Tsutomu OKAZAKI, Motoi Ashida, Hiroji Ozaki, Tsuyoshi Koga, Daisuke Okada
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Patent number: 7863135Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: GrantFiled: February 16, 2010Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventors: Takeshi Sakai, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Patent number: 7816207Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.Type: GrantFiled: March 8, 2010Date of Patent: October 19, 2010Assignee: Renesas Technology Corp.Inventors: Tsutomu Okazaki, Motoi Ashida, Hiroji Ozaki, Tsuyoshi Koga, Daisuke Okada
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Publication number: 20100159687Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.Type: ApplicationFiled: March 8, 2010Publication date: June 24, 2010Applicant: Renesas Technology Corp.Inventors: Tsutomu OKAZAKI, Motoi Ashida, Hiroji Ozaki, Tsuyoshi Koga, Daisuke Okada
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Publication number: 20100144108Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: ApplicationFiled: February 16, 2010Publication date: June 10, 2010Inventors: Takeshi SAKAI, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Patent number: 7709874Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.Type: GrantFiled: January 4, 2007Date of Patent: May 4, 2010Assignee: Renesas Technology Corp.Inventors: Tsutomu Okazaki, Motoi Ashida, Hiroji Ozaki, Tsuyoshi Koga, Daisuke Okada
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Publication number: 20100038700Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: October 16, 2009Publication date: February 18, 2010Inventors: Tsutomu OKAZAKI, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Patent number: 7663176Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: GrantFiled: May 2, 2008Date of Patent: February 16, 2010Assignee: Renesas Technology Corp.Inventors: Takeshi Sakai, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Patent number: 7636253Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: January 16, 2009Date of Patent: December 22, 2009Assignee: Renesas Technology Corp.Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20090122609Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: January 16, 2009Publication date: May 14, 2009Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATA, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
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Patent number: 7502257Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: May 1, 2007Date of Patent: March 10, 2009Assignee: Renesas Technology Corp.Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20080203466Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: ApplicationFiled: May 2, 2008Publication date: August 28, 2008Inventors: Takeshi SAKAI, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada