Abstract: According to one embodiment, an image sensor device includes a sensor array on a semiconductor substrate, the sensor array including blocks, each of the blocks including a pixel and outputting a signal of the pixel; a first insulating layer on the sensor array; semiconductor layers on the first insulating layer; analog-digital converting circuits on the semiconductor layers, the analog-digital converting circuits corresponding to the blocks and processing the signal; a second insulating layer on the first insulating layer and the analog-digital converting circuits; and interconnect portions electrically connecting the analog-digital converting circuits to the blocks via a region between the semiconductor layers, the interconnect portions extending across the first insulating layer and the second insulating layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including Ge; and a metal Ge compound region provided in a surface portion of the semiconductor layer. Sn is included in an interface portion between the semiconductor layer and the metal Ge compound region. A lattice plane of the semiconductor layer matches with a lattice plane of the metal Ge compound region.

Abstract: According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.

Abstract: According to one embodiment, a semiconductor device of a junctionless structure includes a semiconductor layer of a first conductivity type. A pair of source/drain electrodes at a distance is on the semiconductor layer. A gate insulating film is on the semiconductor layer between the source/drain electrodes. A gate electrode is on the gate insulating film. The semiconductor layer has two or more kinds of impurities. One kind of the two or more kinds of impurities is an element selected from a group of chalcogens, and another kind of the two or more kinds of impurities is a first conductivity type impurity.

Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.

Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device including forming a first SiGe layer on an insulating film, processing the first SiGe layer to have an island shape which includes a first region and a second region, the first region having a width larger than a width of the second region in a direction perpendicular to a connecting direction of the second region, subjecting the first SiGe layer having the island shape to thermal oxidation, thereby increasing Ge composition of the first and second region, and setting the Ge composition of the second region to be higher than the Ge composition of the first region, melting the second region having the increased Ge composition by heat treatment, and recrystallizing the melted second region from an interface between the first and second region.

Abstract: According to one embodiment, a method of manufacturing a MOS semiconductor device. In the method, a gate electrode is formed on a gate insulating film provided on a channel region which is a part of an Si layer and which is interposed between a source/drain region, and a film mainly includes of Ge is made to grow on the source/drain region. Then, and the film mainly includes of Ge is made to react with a metal, forming an intermetallic compound film having a depthwise junction position identical to a growth interface of the film mainly includes of Ge.

Abstract: According to one embodiment, a semiconductor device including a tunnel FET, includes a gate electrode, which is formed on a first semiconductor layer formed of Si1?XGeX (0<x?1) through a gate insulating film, a source electrode, which is formed of a compound of a second semiconductor formed mainly using Ge and a metal, a drain electrode, which is formed of a compound of the first semiconductor layer and the metal, and a silicon (Si) thin film, which is formed between the source electrode and the first semiconductor layer. An edge portion of the source electrode and an edge portion of the drain electrode have a positional relationship of Asymmetrical to the gate electrode. The edge portion of the drain electrode is far away from an edge portion of the gate electrode toward a gate external direction compared with the edge portion of the source electrode.

Abstract: According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device including forming a first SiGe layer on an insulating film, processing the first SiGe layer to have an island shape which includes a first region and a second region, the first region having a width larger than a width of the second region in a direction perpendicular to a connecting direction of the second region, subjecting the first SiGe layer having the island shape to thermal oxidation, thereby increasing Ge composition of the first and second region, and setting the Ge composition of the second region to be higher than the Ge composition of the first region, melting the second region having the increased Ge composition by heat treatment, and recrystallizing the melted second region from an interface between the first and second region.

Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.

Abstract: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode.

Abstract: According to one embodiment, a semiconductor device having a Ge— or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.

Abstract: According to one embodiment, a field-effect transistor comprises a gate insulating film which is provided on a part of a Ge-containing substrate and the gate insulating film includes at least a GeO2 layer, a gate electrode which is provided on the gate insulating film, a source-drain region which is provided in the substrate so as to sandwich a channel region under the gate electrode, and a nitrogen-containing region which is formed on both side parts of the gate insulating film.

Abstract: A field effect transistor according to an embodiment includes: a semiconductor layer; a source region and a drain region formed at a distance from each other in the semiconductor layer; a gate insulating film formed on a portion of the semiconductor layer, the portion being located between the source region and the drain region; a gate electrode formed on the gate insulating film; and a gate sidewall formed on at least one of side faces of the gate electrode, the side faces being located on a side of the source region and on a side of the drain region, the gate sidewall being made of a high dielectric material. The source region and the drain region are separately-placed from the corresponding side faces of the gate electrode.

Abstract: According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: According to one embodiment, a method of manufacturing a MOS semiconductor device. In the method, a gate electrode is formed on a gate insulating film provided on a channel region which is a part of an Si layer and which is interposed between a source/drain region, and a film mainly includes of Ge is made to grow on the source/drain region. Then, and the film mainly includes of Ge is made to react with a metal, forming an intermetallic compound film having a depthwise junction position identical to a growth interface of the film mainly includes of Ge.