Abstract: A substrate used for fabricating devices thereon includes an insulating film, and a monocrystal Ge thin layer formed on the insulating film in contact therewith, the monocrystal Ge thin layer having a thickness not more than 6 nm. The monocrystal Ge thin layer has a thickness not less than 2 nm and a compressive strain.

Abstract: A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to form a protective oxide film on a surface of the SiGe layer. Next, the substrate having the protective oxide film is heated in a non-oxidizing atmosphere to a second temperature higher than the first temperature. Further, heat treatment is performed on the substrate thus heated, in an oxidizing atmosphere at a temperature equal to or higher than the second temperature, to form oxide the SiGe layer, make the SiGe layer thinner and increasing Ge concentration in the SiGe layer, thus forming a SiGe layer having the increased Ge concentration.

Abstract: A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y?0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.

Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y?0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.

Abstract: There is here disclosed a semiconductor device manufacturing method comprising a step of forming an island region including a monocrystalline Si1-x-yGexCy layer (1>x>0, 1>y?0) and a peripheral region including an amorphous or polycrystalline Si1-x-yGexCy layer which surrounds the island region on a monocrystalline Si layer on an insulating film, a step of subjecting the respective Si1-x-yGexCy layers to heat treatment, and after the heat treatment and the removal of a surface oxide film, a step of forming a monocrystalline Si1-z-wGezCw layer (1>z?0, 1>w?0) which becomes an element formation region on the island region.

Abstract: A semiconductor device includes a Si substrate, an insulating film formed on onepart of the Si substrate, a bulk Si region grown on other part of the Si substrate other than the insulating film, Si1-xGex (0<x?1) thin film formed on the insulating film in direct contact with the insulating film, and substantially flush with top of the bulk Si region, a first field effect transistor fabricated in the bulk Si region, and a second field effect transistor fabricated in the Si1-xGex thin film.

Abstract: There is here disclosed a semiconductor device manufacturing method comprising a step of forming an island region including a monocrystalline Si1-x-yGexCy layer (1>x>0, 1>y?0) and a peripheral region including an amorphous or polycrystalline Si1-x-yGexCy layer which surrounds the island region on a monocrystalline Si layer on an insulating film, a step of subjecting the respective Si1-x-yGexCy layers to heat treatment, and after the heat treatment and the removal of a surface oxide film, a step of forming a monocrystalline Si1-z-wGezCw layer (1>z?0, 1>w?0) which becomes an element formation region on the island region.

Abstract: A field effect transistor fabricated in a device isolation region includes a Si1-xGex layer (0<x?1) that a lattice strain is relaxed, a strained Si layer formed on the Si1-xGex, a gate electrode insulatively disposed over a part of the strained Si layer, source and drain regions formed in the strained Si layer with the gate electrode being arranged between the source and drain regions; and a Si film covering side walls of the Si1-xGex layer on ends of the device isolation region.

Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

Abstract: A substrate used for fabricating devices thereon includes an insulating film, and a monocrystal Ge thin layer formed on the insulating film in contact therewith, the monocrystal Ge thin layer having a thickness not more than 6 nm. The monocrystal Ge thin layer has a thickness not less than 2 nm and a compressive strain.

Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y≧0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.

Abstract: A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, and having source and drain regions and a channel region therebetween, the area of the channel region being larger than that of the bottom surface of the semiconductor board, which contacts the insulating layer, and a gate electrode formed on the channel region via a gate insulating layer.

Abstract: An integrated circuit device comprises an insulation layer formed on a substrate, a plurality of lattice relaxed SiGe layers each formed in an island form on the insulation layer, wherein a maximum size of the island form thereof is 10 &mgr;m or less, one of a strained Si layer, a strained SiGe layer and a strained Ge layer formed on at least one of the plurality of lattice relaxed SiGe layers, and a field effect transistor having a gate electrode and source and drain regions, wherein the gate electrode is formed on one of the strained Si layer, the strained SiGe layer and the strained Ge layer with a gate insulation film is disposed therebetween, and the source and drain regions is formed to sandwich a channel region formed below the gate electrode with the gate insulation film disposed therebetween.

Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

Abstract: An object of the invention is to provide a complete depletion-mode SOI field-effect transistor in which transistors having different threshold voltages are integrated. A SiGe film having a high Ge composition and a SiGe film having a low Ge composition are formed on an insulating film, and strain-Si films are respectively formed thereon. Transistors including channel regions in the strain-Si films obtained as a result of this are formed, so that the transistors having different threshold voltages can be integrated.

Abstract: A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, and having source and drain regions and a channel region therebetween, the area of the channel region being larger than that of the bottom surface of the semiconductor board, which contacts the insulating layer, and a gate electrode formed on the channel region via a gate insulating layer.

Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

Abstract: High-speed and low-power-consuming transistors such as field effect transistors having strained Si channels and hetero-bipolar transistors are integrated with each other. Used here is a complex structure in which an MOSFET having a thin-film SiGe buffer layer and a strained Si channel are laminated on an insulating film and an HBT having an SiGe base layer formed on a thin-film SiGe layer by epitaxial growth and an Si emitter layer formed on the SiGe base layer are combined with each other. The thin-film SiGe layer formed on the insulating film of the MOSFET is made thinner than the counterpart of the HBT. The thin-film SiGe layer formed on the insulating film of the MOSFET has Ge concentration higher than that of the counterpart of the HBT.

Abstract: An integrated circuit device comprises an insulation layer formed on a substrate, a plurality of lattice relaxed SiGe layers each formed in an island form on the insulation layer, wherein a maximum size of the island form thereof is 10 &mgr;m or less, one of a strained Si layer, a strained SiGe layer and a strained Ge layer formed on at least one of the plurality of lattice relaxed SiGe layers, and a field effect transistor having a gate electrode and source and drain regions, wherein the gate electrode is formed on one of the strained Si layer, the strained SiGe layer and the strained Ge layer with a gate insulation film is disposed therebetween, and the source and drain regions is formed to sandwich a channel region formed below the gate electrode with the gate insulation film disposed therebetween.