Patents by Inventor Tsutomu Tomioka

Tsutomu Tomioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11402863
    Abstract: Provided is a reference voltage circuit including a Zener diode having a cathode connected to a current source via a first node, and an anode connected to a ground point; a first resistor having one end connected to the first node; a second resistor having one end connected to another end of the first resistor; a first diode having an anode connected to another end of the second resistor via a second node, and a cathode connected to the ground point; and a current control circuit configured to generate a control current corresponding to an anode voltage of the first diode so that the current source supplies a reference current corresponding to the control current to the first diode.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: August 2, 2022
    Assignee: ABLIC INC.
    Inventor: Tsutomu Tomioka
  • Publication number: 20220137660
    Abstract: A reference voltage circuit includes: a first and a second NPN transistor having a collector and a base shorted and diode-connected, the second NPN transistor having an emitter connected to a first potential node and operating at a higher current density; a first resistor connected in series with the first NPN transistor; a second resistor having one end connected to a circuit with the first NPN transistor and the first resistor connected in series; a third resistor having one end connected to the collector of the second NPN transistor; a connection point to which the other ends of the second and the third resistor are connected; an arithmetic amplifier circuit having an inverting input terminal, a non-inverting input terminal, and an output terminal respectively connected to the second resistor, the third resistor, and the connection point; and a current supply circuit connected to the collector of the first NPN transistor.
    Type: Application
    Filed: September 29, 2021
    Publication date: May 5, 2022
    Applicant: ABLIC Inc.
    Inventors: Hideyuki SAWAI, Tsutomu TOMIOKA
  • Publication number: 20210193649
    Abstract: An electrostatic protection circuit and a semiconductor device include: a first diode whose anode is connected to a signal terminal; a second diode whose cathode is connected to a cathode of the first diode and whose anode is connected to a GND terminal; and a depletion type MOS transistor connected in parallel with the first diode.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 24, 2021
    Inventor: Tsutomu TOMIOKA
  • Patent number: 11025047
    Abstract: Provided is a backflow prevention circuit including a backflow prevention transistor as a p-channel MOS transistor interposed in series between an input terminal to which a power supply voltage is supplied, and an output-stage transistor as a p-channel MOS transistor, configured to supply an output voltage from an output terminal, and a backflow prevention control circuit configured to turn off the backflow prevention transistor if the output voltage exceeds the power supply voltage. The backflow prevention control circuit includes a first transistor, a first current source circuit, and a level shift circuit.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: June 1, 2021
    Assignee: ABLIC INC.
    Inventors: Tsutomu Tomioka, Tadakatsu Kuroda
  • Patent number: 11012041
    Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: May 18, 2021
    Assignee: ABLIC INC.
    Inventors: Hideyuki Sawai, Tsutomu Tomioka, Tadakatsu Kuroda
  • Patent number: 10914783
    Abstract: A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 9, 2021
    Assignee: ABLIC INC.
    Inventors: Tadakatsu Kuroda, Tsutomu Tomioka, Hideyuki Sawai
  • Publication number: 20210034092
    Abstract: Provided is a reference voltage circuit including a Zener diode having a cathode connected to a current source via a first node, and an anode connected to a ground point; a first resistor having one end connected to the first node; a second resistor having one end connected to another end of the first resistor; a first diode having an anode connected to another end of the second resistor via a second node, and a cathode connected to the ground point; and a current control circuit configured to generate a control current corresponding to an anode voltage of the first diode so that the current source supplies a reference current corresponding to the control current to the first diode.
    Type: Application
    Filed: July 16, 2020
    Publication date: February 4, 2021
    Inventor: Tsutomu TOMIOKA
  • Patent number: 10831219
    Abstract: A voltage regulator includes an error amplifier circuit which controls a gate voltage of an output transistor, an overcurrent protection circuit which prevents an overcurrent of the output transistor, and a protection circuit which detects a negative voltage of an output terminal and controls a gate voltage of the output transistor to suppress an overcurrent. The protection circuit includes a MOS transistor which controls the gate voltage of the output transistor, a clamp circuit connected to a gate of the MOS transistor, a semiconductor element having an N-type region connected to the clamp circuit, and a parasitic bipolar transistor constructed from an N-type region connected to the output terminal as an emitter, a P-type substrate as a base, and the N-type region of the semiconductor element as a collector.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 10, 2020
    Assignee: ABLIC INC.
    Inventors: Tsutomu Tomioka, Tadakatsu Kuroda, Masakazu Sugiura
  • Patent number: 10637344
    Abstract: A source-grounded amplifier circuit supplied with a signal of an error amplifier circuit, and an output transistor supplied with a control voltage of the source-grounded amplifier circuit are provided. The source-grounded amplifier circuit has, in a signal path, a current limiting circuit including a cascode circuit controlled by a voltage having a positive temperature coefficient. A voltage regulator capable of reducing a dropout voltage of an output voltage without exceeding a gate breakdown voltage of the output transistor is provided.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: April 28, 2020
    Assignee: ABLIC INC.
    Inventors: Tsutomu Tomioka, Masakazu Sugiura
  • Patent number: 10613562
    Abstract: A voltage regulator includes a first switch connected between a first input terminal of an error amplifier circuit and an input terminal of the voltage regulator, a second switch connected between a second input terminal of the error amplifier circuit and an output terminal of the voltage regulator, a third switch connected between the first input terminal and the second input terminal, and a short fault detection circuit which detects a short fault of the output terminal, based on an output voltage of the voltage regulator.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 7, 2020
    Assignee: ABLIC INC.
    Inventors: Tadakatsu Kuroda, Tsutomu Tomioka
  • Patent number: 10591942
    Abstract: A voltage regulator which includes a differential amplifier circuit containing a first and second input transistors, controlling a gate-source voltage in each of the first and second input transistors including: a current source configured to drive the differential amplifier circuit; the first input transistor containing a gate; the second input transistor containing a gate; and a voltage controller including at least one of a first voltage control circuit to control a voltage at a tail connection point, a second voltage control circuit to control the voltage at the gate of the first input transistor, a third voltage control circuit to control the voltage at the tail connection point, and a fourth voltage control circuit to control the voltage at the gate of the second input transistor.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 17, 2020
    Assignee: ABLIC INC.
    Inventors: Tadakatsu Kuroda, Tsutomu Tomioka, Hideyuki Sawai, Michiyasu Deguchi
  • Patent number: 10571942
    Abstract: The overcurrent limiting circuit includes: a limit voltage generation circuit generating a limit voltage which defines the limit current value as a current corresponding to a magnitude of a power supply voltage; a source follower having an output terminal and an input terminal which is connected to a gate of the output stage transistor, and configured to supply from the output terminal a voltage level-shifted from a voltage provided to the input terminal; an error amplifier circuit amplifying a difference between the limit voltage and the voltage supplied from the source follower; and a gate voltage adjustment transistor having a gate to which the voltage supplied from the error amplifier circuit is applied, and controlling a gate voltage applied to the gate of the output stage transistor.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: February 25, 2020
    Assignee: ABLIC INC.
    Inventor: Tsutomu Tomioka
  • Publication number: 20200019200
    Abstract: A voltage regulator which includes a differential amplifier circuit containing a first and second input transistors, controlling a gate-source voltage in each of the first and second input transistors including: a current source configured to drive the differential amplifier circuit; the first input transistor containing a gate; the second input transistor containing a gate; and a voltage controller including at least one of a first voltage control circuit to control a voltage at a tail connection point, a second voltage control circuit to control the voltage at the gate of the first input transistor, a third voltage control circuit to control the voltage at the tail connection point, and a fourth voltage control circuit to control the voltage at the gate of the second input transistor.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 16, 2020
    Inventors: Tadakatsu KURODA, Tsutomu TOMIOKA, Hideyuki SAWAI, Michiyasu DEGUCHI
  • Publication number: 20200014348
    Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.
    Type: Application
    Filed: June 18, 2019
    Publication date: January 9, 2020
    Inventors: Hideyuki SAWAI, Tsutomu TOMIOKA, Tadakatsu KURODA
  • Publication number: 20190393692
    Abstract: Provided is a backflow prevention circuit including a backflow prevention transistor as a p-channel MOS transistor interposed in series between an input terminal to which a power supply voltage is supplied, and an output-stage transistor as a p-channel MOS transistor, configured to supply an output voltage from an output terminal, and a backflow prevention control circuit configured to turn off the backflow prevention transistor if the output voltage exceeds the power supply voltage. The backflow prevention control circuit includes a first transistor, a first current source circuit, and a level shift circuit.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 26, 2019
    Inventors: Tsutomu Tomioka, Tadakatsu Kuroda
  • Patent number: 10444777
    Abstract: A reverse-current-prevention circuit includes a reverse-current-prevention transistor of a P-channel MOS transistor inserted between an input terminal supplied with a power supply voltage and an output stage transistor of a P-channel MOS transistor providing an output voltage from an output terminal, and a reverse-current-prevention controller configured to turn the reverse-current-prevention transistor from on to off according to exceedance of the output voltage to the power supply voltage. The reverse-current-prevention controller includes a first transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to the output terminal and the input terminal, and a second transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to a drain of the first transistor and a gate of the reverse-current-prevention transistor, and a drain grounded.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 15, 2019
    Assignee: Ablic Inc.
    Inventor: Tsutomu Tomioka
  • Publication number: 20190302816
    Abstract: A voltage regulator includes an error amplifier circuit which controls a gate voltage of an output transistor, an overcurrent protection circuit which prevents an overcurrent of the output transistor, and a protection circuit which detects a negative voltage of an output terminal and controls a gate voltage of the output transistor to suppress an overcurrent. The protection circuit includes a MOS transistor which controls the gate voltage of the output transistor, a clamp circuit connected to a gate of the MOS transistor, a semiconductor element having an N-type region connected to the clamp circuit, and a parasitic bipolar transistor constructed from an N-type region connected to the output terminal as an emitter, a P-type substrate as a base, and the N-type region of the semiconductor element as a collector.
    Type: Application
    Filed: February 28, 2019
    Publication date: October 3, 2019
    Inventors: Tsutomu TOMIOKA, Tadakatsu Kuroda, Masakazu Sugiura
  • Publication number: 20190277908
    Abstract: A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.
    Type: Application
    Filed: January 25, 2019
    Publication date: September 12, 2019
    Inventors: Tadakatsu KURODA, Tsutomu Tomioka, Hideyuki Sawai
  • Publication number: 20190265739
    Abstract: A voltage regulator includes a first switch connected between a first input terminal of an error amplifier circuit and an input terminal of the voltage regulator, a second switch connected between a second input terminal of the error amplifier circuit and an output terminal of the voltage regulator, a third switch connected between the first input terminal and the second input terminal, and a short fault detection circuit which detects a short fault of the output terminal, based on an output voltage of the voltage regulator.
    Type: Application
    Filed: January 16, 2019
    Publication date: August 29, 2019
    Inventors: Tadakatsu Kuroda, Tsutomu Tomioka
  • Publication number: 20190243400
    Abstract: The overcurrent limiting circuit includes: a limit voltage generation circuit generating a limit voltage which defines the limit current value as a current corresponding to a magnitude of a power supply voltage; a source follower having an output terminal and an input terminal which is connected to a gate of the output stage transistor, and configured to supply from the output terminal a voltage level-shifted from a voltage provided to the input terminal; an error amplifier circuit amplifying a difference between the limit voltage and the voltage supplied from the source follower; and a gate voltage adjustment transistor having a gate to which the voltage supplied from the error amplifier circuit is applied, and controlling a gate voltage applied to the gate of the output stage transistor.
    Type: Application
    Filed: January 4, 2019
    Publication date: August 8, 2019
    Inventor: Tsutomu TOMIOKA