Abstract: Provided is a backflow prevention circuit including a backflow prevention transistor as a p-channel MOS transistor interposed in series between an input terminal to which a power supply voltage is supplied, and an output-stage transistor as a p-channel MOS transistor, configured to supply an output voltage from an output terminal, and a backflow prevention control circuit configured to turn off the backflow prevention transistor if the output voltage exceeds the power supply voltage. The backflow prevention control circuit includes a first transistor, a first current source circuit, and a level shift circuit.

Abstract: A reverse-current-prevention circuit includes a reverse-current-prevention transistor of a P-channel MOS transistor inserted between an input terminal supplied with a power supply voltage and an output stage transistor of a P-channel MOS transistor providing an output voltage from an output terminal, and a reverse-current-prevention controller configured to turn the reverse-current-prevention transistor from on to off according to exceedance of the output voltage to the power supply voltage. The reverse-current-prevention controller includes a first transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to the output terminal and the input terminal, and a second transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to a drain of the first transistor and a gate of the reverse-current-prevention transistor, and a drain grounded.

Abstract: A voltage regulator includes an error amplifier circuit which controls a gate voltage of an output transistor, an overcurrent protection circuit which prevents an overcurrent of the output transistor, and a protection circuit which detects a negative voltage of an output terminal and controls a gate voltage of the output transistor to suppress an overcurrent. The protection circuit includes a MOS transistor which controls the gate voltage of the output transistor, a clamp circuit connected to a gate of the MOS transistor, a semiconductor element having an N-type region connected to the clamp circuit, and a parasitic bipolar transistor constructed from an N-type region connected to the output terminal as an emitter, a P-type substrate as a base, and the N-type region of the semiconductor element as a collector.

Abstract: A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.

Abstract: A voltage regulator includes a first switch connected between a first input terminal of an error amplifier circuit and an input terminal of the voltage regulator, a second switch connected between a second input terminal of the error amplifier circuit and an output terminal of the voltage regulator, a third switch connected between the first input terminal and the second input terminal, and a short fault detection circuit which detects a short fault of the output terminal, based on an output voltage of the voltage regulator.

Abstract: The overcurrent limiting circuit includes: a limit voltage generation circuit generating a limit voltage which defines the limit current value as a current corresponding to a magnitude of a power supply voltage; a source follower having an output terminal and an input terminal which is connected to a gate of the output stage transistor, and configured to supply from the output terminal a voltage level-shifted from a voltage provided to the input terminal; an error amplifier circuit amplifying a difference between the limit voltage and the voltage supplied from the source follower; and a gate voltage adjustment transistor having a gate to which the voltage supplied from the error amplifier circuit is applied, and controlling a gate voltage applied to the gate of the output stage transistor.

Abstract: A reverse-current-prevention circuit includes a reverse-current-prevention transistor of a P-channel MOS transistor inserted between an input terminal supplied with a power supply voltage and an output stage transistor of a P-channel MOS transistor providing an output voltage from an output terminal, and a reverse-current-prevention controller configured to turn the reverse-current-prevention transistor from on to off according to exceedance of the output voltage to the power supply voltage. The reverse-current-prevention controller includes a first transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to the output terminal and the input terminal, and a second transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to a drain of the first transistor and a gate of the reverse-current-prevention transistor, and a drain grounded.

Abstract: To provide an input circuit which avoids power supply voltage dependency of a threshold of the input circuit when an output signal is transited. There is provided an input circuit equipped with an input transistor and a current source connected in series between a first power supply and a second power supply. The input circuit is configured in such a manner that an input signal is inputted to a gate of the input transistor and a signal of a connection point between the input transistor and the current source is outputted as an output signal, and a current value of the current source is changed based on the output signal.

Abstract: A source-grounded amplifier circuit supplied with a signal of an error amplifier circuit, and an output transistor supplied with a control voltage of the source-grounded amplifier circuit are provided. The source-grounded amplifier circuit has, in a signal path, a current limiting circuit including a cascode circuit controlled by a voltage having a positive temperature coefficient. A voltage regulator capable of reducing a dropout voltage of an output voltage without exceeding a gate breakdown voltage of the output transistor is provided.

Abstract: Provided is an overheat detection circuit configured to accurately detect a temperature of a semiconductor device even at high temperature and thus avoid outputting an erroneous detection result. The overheat detection circuit includes: a PN junction element, being a temperature sensitive element; a constant current circuit configured to supply the PN junction element with a bias current; a comparator configured to compare a voltage generated at the PN junction element and a reference voltage; a second PN junction element configured to cause a leakage current to flow through a reference voltage circuit at high temperature; and a third PN junction element configured to bypass a leakage current of the constant current circuit at the high temperature.

Abstract: Provided is a voltage regulator configured to suppress a fluctuation in output voltage even when a power supply voltage fluctuates, thereby realizing stable operation thereof. The voltage regulator includes a control circuit including a first input terminal connected to a drain of an output transistor, a second input terminal connected to a power supply terminal, an overshoot detection circuit connected to the first input terminal, and a power supply voltage detection circuit connected to the second input terminal, and being configured to cause a boost current to flow through an error amplifier circuit when an output voltage and a power supply voltage largely fluctuate with respect to a predetermined voltage.

Abstract: Provided is a voltage regulator configured to suppress a variation of an output voltage so as to stably operate even when a power supply voltage varies. The voltage regulator includes a control circuit having an input terminal connected to a drain of an output transistor, and an output terminal connected to an error amplifier circuit. The control circuit is configured to cause a boost current to flow through an error amplifier circuit when the output voltage varies beyond a predetermined value.

Abstract: To provide a reference voltage circuit capable of outputting a reference voltage excellent in temperature characteristic. A reference voltage circuit includes a first constant current circuit, a first transistor of a first conductivity type which has a source connected to the first constant current circuit and is operated as a first stage source follower, a second constant current circuit, and a second transistor of a second conductivity type which has a gate connected to the source of the first transistor and a source connected to the second constant current circuit and is operated as a second stage source follower. The reference voltage circuit is configured to output a reference voltage from the source of the second transistor.

Abstract: Provided is a voltage regulator including a clamp circuit capable of protecting a gate of an output transistor without limiting a drivability of the output transistor. The voltage regulator includes a level shift circuit having an input terminal connected to the gate of the output transistor and an output terminal connected to an input of the clamp circuit. The clamp circuit is controlled by an output voltage of the level shift circuit.

Abstract: Provided is a voltage regulator capable of applying an optimal overshoot suppression unit depending on states. The voltage regulator includes: an amplifier for controlling an output transistor based on a voltage obtained by amplifying a difference between a divided voltage and a reference voltage; a first overshoot suppression unit for controlling a gate voltage of the output transistor, to thereby suppress overshoot of the output voltage; a second overshoot suppression unit for controlling an operating current of the amplifier, to thereby suppress the overshoot of the output voltage; and a control circuit. The control circuit is configured to turn on the first overshoot suppression unit immediately after the voltage regulator is powered on, and turn off the first overshoot suppression unit under a state in which the output voltage is stable.

Abstract: To provide an input circuit which avoids power supply voltage dependency of a threshold of the input circuit when an output signal is transited. There is provided an input circuit equipped with an input transistor and a current source connected in series between a first power supply and a second power supply. The input circuit is configured in such a manner that an input signal is inputted to a gate of the input transistor and a signal of a connection point between the input transistor and the current source is outputted as an output signal, and a current value of the current source is changed based on the output signal.

Abstract: Provided is an amplifier circuit including an NMOS transistor having a low drain breakdown voltage and an NMOS transistor having a high drain breakdown voltage connected in series thereto, and capable of preventing breakdown of a drain of the NMOS transistor having a low drain breakdown voltage. A clamp circuit configured to limit a drain voltage of the NMOS transistor having a low drain breakdown voltage is connected to the drain thereof.

Abstract: Provided is a voltage regulator configured to suppress a fluctuation in output voltage even when a power supply voltage fluctuates, thereby realizing stable operation thereof. The voltage regulator includes a control circuit including a first input terminal connected to a drain of an output transistor, a second input terminal connected to a power supply terminal, an overshoot detection circuit connected to the first input terminal, and a power supply voltage detection circuit connected to the second input terminal, and being configured to cause a boost current to flow through an error amplifier circuit when an output voltage and a power supply voltage largely fluctuate with respect to a predetermined voltage.

Abstract: To provide a voltage regulator capable of preventing a reduction in output voltage and an increase in output noise in a steady state without performing suppression of an overshoot. A voltage regulator is equipped with an overshoot detection circuit which detects an overshoot on the basis of an output voltage, an overshoot suppression circuit which controls an output terminal of an error amplifier circuit, based on the output of the overshoot detection circuit, and a driver state discrimination circuit which discriminates the state of an output transistor, based on an output voltage of the error amplifier circuit. The driver state discrimination circuit is configured to control the operation of the overshoot suppression circuit.

Abstract: A voltage regulator is provided which can suppress an occurrence of overshooting in an output voltage at the time of starting a power source with a source voltage or the like. The voltage regulator includes an error amplifier circuit, an overshooting control circuit that is connected to the gate of an output transistor, and an ON/OFF circuit that controls ON and OFF states of at least the error amplifier circuit. Here, the ON/OFF circuit controls the overshooting control circuit so as to turn on the output transistor when a predetermined time passes after at least the error amplifier circuit is turned on at the time of starting the voltage regulator.