Abstract: A dummy word line driving circuit for a MOS dynamic RAM comprises a dummy word line controller connected to each end of a pair of dummy word lines. A sub-decode signal which is opposite to the one inputted to a dummy word driver and a dummy set signal for writing a bit line information into a not-selected dummy cell are inputted to the dummy word line controller. Means for applying a dummy equalizing signal is connected to two full-sized dummy cells, for equalizing the two before the dummy word line is driven. The two full-sized dummy cells are equalized by the signal, resulting in a charge amount, which is to be a reference value, of a half of a full-sized memory cell.

Abstract: A semiconductor memory device comprises a data input switching circuit (20) connected between the output side of a write check bit generating circuit (2) and the input side of a check bit memory cell array (32), a data output switching circuit (30) connected to the input side of an address decoder (9), and an address switching circuit (10) connected to the output side of the address decoder (9). When a test mode is entered, the data input switching circuit (2), data output switching circuit (30) and address switching circuit (10) connect a data input signal line (l), data output signal line (m) and address signal line (n), respectively, to the check bit memory cell array (32), enabling the check bit memory cell array (32) to be accessed from the outside.

Abstract: A first precharging and equalizing circuit (7) precharges and equalizes I/O buses (10 and 10') in advance to selection of bit lines, and following thereto, a second precharging and equalizing circuit (12) precharges and equalizes the I/O buses (10 and 10') during driving operation of a sense amplifier (2). Thus, potential levels of the I/O Buses (10 and 10') are prevented from being changed by vibration of the output level of the sense amplifier (2) transmitted to the I/O buses (10 and 10') through parasitic capacitance (8) during driving operation of the sense amplifier (2).

Abstract: A dynamic memory device including 1-transistor, 1-capacitor type dynamic memory cell, wherein a half voltage of the writing voltage is applied to a cell plate, and a constant voltage is applied to the substrate.

Abstract: A semiconductor memory device is operable selectively in a page mode or a nibble mode, depending upon an external mode selection signal. In the page mode of operation a row address is supplied to the memory with subsequently supplied column addresses corresponding on a one-to-one basis with data to be stored into or read from memory. In the nibble mode of operation, the memory sequentially reads from or writes to four adjacent memory cells for each column address supplied.

Abstract: A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.

Abstract: An insulated gate field-effect transistor (MOS.multidot.FET) formed as a basic element of an integrated circuit formed together with a substrate bias circuit in a semiconductor substrate having negative potential. In the substrate bias circuit, semiconductor regions (p.sup.+ -regions) having impurity concentrations higher than that of the semiconductor substrate (p-type) are formed between the semiconductor regions (n.sup.+ -region) and the semiconductor substrate (p-type) to form n.sup.+ p.sup.+ p-diodes.

Abstract: An insulated gate semiconductor is prepared by forming auxiliary regions for source-drain regions having a shallow junction by a self-aligning process using a gate electrode as a mask; covering it with a thick insulating membrane for surface protection; forming a contact hole for bonding an electrode in the thick insulating membrane; and forming source-drain regions having deep junction through the contact hole and bonding an electrode metal to it in the contact hole.