Abstract: A differential VCO includes a ring oscillator with a plurality of differential buffers connected in a ring, a bias circuit including a replica circuit of the differential buffers, and a differential gain increasing circuit for increasing differential gain of the differential buffers. Even when the differential gain of the differential buffer lowers as a result of obtaining a clock signal of higher frequency, the ring oscillator oscillates smooth.

Abstract: A duty ratio can be corrected to 1:1 without affecting the operation of a PLL or DLL circuit. A rising-edge control circuit (1a) generates a signal (S10) by inverting a signal (S6), and varies a time required for a high to low transition of the signal (S10). A comparator (A1) causes a transition of a signal (S2) when the signal (S10) becomes less than a reference value (Vref), so the duty ratio of the signal (S2) varies according to the length of its fall time. A duty-ratio detecting circuit (2) is a charge pump for drawing or passing a constant amount of current according to a voltage of the signal (S2). A duty-ratio correction filter (3) converts a signal (S8) obtained from the duty-ratio detecting circuit (2) into a smooth voltage signal (S9). This signal (S9) becomes a feedback signal to the rising-edge control circuit (1a) for correcting the duty ratio of the signal (S2) to 1:1.

Abstract: Transistors (MP1 and MP2) supply a current (I.sub.0) for nodes (K and L), respectively. Transistors (MN10 and MN11) draw the same current from nodes (K and L), respectively. A parallel connection of serial connections (N1 and N2) draws a current (I.sub.1) from the node (K) only when an exclusive OR of clocks (S1 and S2) is "H". On the other hand, a parallel connection of serial connections (N3 and N4) draws a current (I.sub.1) from the node (L) only when the exclusive OR of clocks (S1 and S2) is "L". When the current (I.sub.1) is drawn from the node (K), the current (I.sub.1) flows out from the node (L) and when the current (I.sub.1) is drawn from the node (L), the current (I.sub.1) flows into the node (L). In the serial connections (N1 to N4), each of the clocks (S1 and S2) and their inverted signals (S1B and S2B) is applied to one of the gates of the transistors (MN1 to MN8) and therefore a uniform input load is obtained.

Abstract: In a synchronous semiconductor memory device in which an internal clock signal from an internal timing clock signal generating circuit is branched in the form of a tree by driver circuits and applied to output buffers and data are output in synchronization with the internal clock signal, the driver circuit of the first stage is constituted by an NAND gate and an inverter. When output is to be temporarily stopped, an enabling signal is set to "L" level, so that the NAND gate is closed, output of the clock signal to each driver circuit is stopped, and thus power consumption is reduced.

Abstract: Provided is a DLL circuit that can execute a precise delay synchronization operation without increasing the variable delay time range of a delay line. The DLL circuit comprises a phase comparator (3), a charge pump (6), an LPF (8) and a delay line (9), and operates to match phases of an input signal (CLKIN) and a feedback signal (FBCLK). The phase comparator (3) always outputs a phase comparison result that causes a delay time of the delay line (9) to increase, at the time of initial operation after a reset operation. The LPF (8) outputs a delay adjusting signal (S8) indicating that a delay time due to the delay line (9) becomes the minimum, in executing a reset.

Abstract: A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.

Abstract: It is an object to realize a synchronization circuit with small size and low consumption power which enables capturing and phasing of external data without running external clock in parallel. Internal clock (2) is delayed by a delay line (1) to produce delay clocks (3), and one of the delay clocks (3) having its rise almost corresponding to that of an external data signal (6) becomes a select clock (5). An elastic store circuit (7) is a circuit which controls a row of D-latches with a row of C elements. Thus the elastic store circuit (7) captures the external data signal (6) with enough set up hold time at timing of the select clock (5) and then outputs the captured external data as an internal data signal (8) in synchronization with the internal clock (2).

Abstract: A glycerin derivative having the following formula (I) or (I') and a pharmacologically acceptable salt thereof are useful to treat diseases caused by the platelet activating factor.

Abstract: A glycerin derivative having the following formula (I) or (I') and a pharmacologically acceptable salt thereof are useful to treat diseases caused by the platelet activating factor.

Abstract: A quinone derivative useful in the treatment of hepatic diseases defined by the general formula: ##STR1## where X and Y may be the same or different from each other and are each a hydroxyl group, a group represented by the formula --(--OCH.sub.2 --).sub.n --OR.sup.6, wherein n is 0 or 1 and R.sup.6 is a lower alkyl group, or an acyl group.

Abstract: A glycerin derivative having the following formula (I) or (I') and a pharmacologically acceptable salt thereof are useful to treat diseases caused by the platelet activating factor.

Abstract: A quinone derivative useful in the treatment of hepatic diseases defined by the general formula: ##STR1## where R1 is selected from the group consisting of alkyl, alkenly, alkynyl or heterocycle, R2 is a substituted nitrogen containing radical wherein the substituents on said nitrogen are selected from the group consisting of hydrogen, substituted or unsubstituted lower alkyl or heterocycles, and where said nitrogen may be a ring heteroatom, and R3, R4 and R5, may be the same or different and each are hydrogen, lower alkyl or lower alkoxy groups.

Abstract: A glycerin derivative having the following formula (I) or (I') and a pharmacologically acceptable salt thereof are useful to treat diseases caused by the platelet activating factor.