Patents by Inventor Tsuyoshi Hashimoto

Tsuyoshi Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916513
    Abstract: An oscillator in which crosstalk can be reduced is provided. An oscillator includes a SQUID, a transmission line connected to the SQUID, a ground plane, and a first connection circuit disposed in a vicinity of a node of an electric field of a standing wave that is generated when the oscillator is oscillating, the first connection circuit connecting parts of the ground plane located on both sides of the transmission line to each other.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: February 27, 2024
    Assignee: NEC CORPORATION
    Inventors: Yoshihito Hashimoto, Tsuyoshi Yamamoto, Tomohiro Yamaji
  • Patent number: 11533006
    Abstract: A motor controlling device configured to control an on-board motor is provided, which includes an H-bridge type drive circuit comprised of first switching elements and configured to drive the on-board motor, and a controlling circuit configured to control the on-board motor by controlling the drive circuit, the controlling circuit carrying out an ON control of one of the first switching elements connected to ground, when not operating the on-board motor.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 20, 2022
    Assignees: MAZDA MOTOR CORPORATION, U-SHIN LTD
    Inventors: Tsuyoshi Hashimoto, Naoki Takasuka, Shinya Kanayama, Kazuhiko Obatake, Hideyuki Osumi, Makoto Kobayashi
  • Publication number: 20210249976
    Abstract: A motor controlling device configured to control an on-board motor is provided, which includes an H-bridge type drive circuit comprised of first switching elements and configured to drive the on-board motor, and a controlling circuit configured to control the on-board motor by controlling the drive circuit, the controlling circuit carrying out an ON control of one of the first switching elements connected to ground, when not operating the on-board motor.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 12, 2021
    Inventors: Tsuyoshi Hashimoto, Naoki Takasuka, Shinya Kanayama, Kazuhiko Obatake, Hideyuki Osumi, Makoto Kobayashi
  • Patent number: 11036549
    Abstract: A parallel processing apparatus includes: a memory; and a processor coupled to the memory, the processor is configured to: acquire a first time and a second time; divide a plurality of nodes into a plurality of groups; generate a plurality of schedule candidates each which assigns time zones corresponding to a length of time used to perform a maintenance operation at one or more nodes included in the plurality of groups in a time period from the first time to the second time to the plurality of groups such that no overlap occurs among the plurality of groups; evaluate the plurality of schedule candidates based on one or more process execution schedules of the one or more nodes in the time period; and output one schedule candidate of the plurality of schedule candidates based on a result of the evaluation.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: June 15, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Kazuhiro Matsuyama, Tsuyoshi Hashimoto
  • Patent number: 11023281
    Abstract: A parallel processing apparatus includes a memory and a processor. The memory stores a program and the processor is coupled to the memory. The processor calculates, based on a number of nodes to be used in execution of respective jobs that are waiting to be executed and a scheduled execution time period for execution of the respective jobs, an execution scale of the respective jobs and allocates the respective jobs to an area in which a number of problem nodes that have a high failure possibility is small from among a plurality of areas into which a region in which a plurality of nodes are disposed is partitioned and divided. The allocation of the jobs is performed in descending order of the execution scale beginning with the job whose execution scale is the largest.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 1, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Ryosuke Kokubo, Tsuyoshi Hashimoto
  • Patent number: 10635522
    Abstract: A processor-fault reproduction method includes: determining a heating time of a processor taken using a heating program which heats the processor to a fault occurrence temperature when a fault occurs from a current temperature based on first information regarding the current temperature of the processor, second information regarding a power consumption value and a temperature of the processor before the fault occurs and a refrigerant temperature of a cooling medium to cool the processor, third information regarding the fault occurrence temperature, and fourth information regarding a power consumption value of the processor during execution of the heating program; determining an execution time by adding a fault reproduction time taken by a fault reproducing program which reproduces a state of the processor when the fault occurs to the heating time; and reporting the execution time to a job scheduler with a request to execute the heating and fault reproducing programs.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: April 28, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Jumpei Kubota, Tsuyoshi Hashimoto
  • Patent number: 10613953
    Abstract: A start test method executed by a system including a calculation device and a management device that manages failure information on the calculation device, the start test method includes storing, by a first processor included in the management device, a failure rate that has been calculated for each of parts of the calculation device based on the failure information received from the calculation device as performance information, associating with time information and a part of the calculation device; obtaining a failure rate of each of the parts at a time of start of the calculation device based on the performance information and a time when the calculation device is to be started; notifying the calculation device of the obtained failure rate; and executing, by a second processor included in the calculation device, a start test of the calculation device in accordance with the notified failure rate.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: April 7, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Taku Komorida, Atsushi Takami, Masato Fukumori, Haruhiko Ueno, Tsuyoshi Hashimoto
  • Patent number: 10599472
    Abstract: An information processing apparatus includes: a processor performs a scheduling process of scheduling a job for nodes and including: calculating, when one node executes a first job, a job execution end time when execution of the first job is completed by referring an execution history in which an execution time of a job is recorded; acquiring, from a load management node that manages a load of a metadata-process execution node which performing metadata processing to access metadata of a file among the nodes, the load of the metadata-process execution node at the job execution end time; and generating, when the load is equal to or more than a threshold, schedule data to cause a staging execution node which performs the metadata processing produced by staging, at the job execution end time, the metadata processing based on staging to a file having an execution result of the first job.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: March 24, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Atsushi Nukariya, Tsuyoshi Hashimoto
  • Patent number: 10594591
    Abstract: An information processing apparatus is configured to receive a request for communication between a first node and a second node included in a parallel calculation system, acquire job execution information relating a job to be executed by the parallel calculation system, generate connected graph information based on first information on the first node, second information on the second node, the job execution information, and topology information indicating a topology of the plurality of nodes, generate, based on the connected graph information, route information indicating a plurality of routes used when the communication between the first node and the second node is executed, specify, based on the route information, a route having the lowest passing cost among the plurality of routes; and specify a node included in the specified route as a relay node based on positions of the plurality of nodes in the specified route.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 17, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Akio Houjyo, Tsuyoshi Hashimoto
  • Patent number: 10503722
    Abstract: A log management apparatus includes a memory configured to store log information and identification information in association with each other, and a processor configured to store, in association with first identification information in the memory, first log information output, before a semaphore returns to an initial value but after the semaphore decreases from the initial value, from a program employing the semaphore, associate the first identification information with information relative to deletion of the log information when the semaphore has returned to the initial value, and perform deletion of the first log information among the log information stored in the memory in accordance with the first identification information associated with the information.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 10, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Hiroki Yokota, Tsuyoshi Hashimoto
  • Patent number: 10491491
    Abstract: An information processing method for a computer having a memory and a processor coupled to the memory, and the computer is coupled between a plurality of transmission nodes and a reception node. The method including: calculating coefficients of an equation, the coefficients corresponding to a number of transmission nodes having an abnormality among a plurality of transmission nodes, based on a numeric value including state information of transmission nodes having the abnormality and identification information for identifying the transmission nodes having the abnormality; and transmitting the coefficients to a reception node that extracts the numeric value from a solution of the equation using the coefficients.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: November 26, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Reiji Masaki, Tsuyoshi Hashimoto
  • Patent number: 10437494
    Abstract: A storage control apparatus configured to control a storage apparatus accessed by an information processing apparatus when the information processing apparatus executes a job, the storage control apparatus includes a memory configured to store plan information that indicates a plan in which the information processing apparatus executes the job and history information that indicates an history of access from the information processing apparatus to the storage apparatus when the information processing apparatus executes the job, and a processor coupled to the memory and configured to perform, based on the plan information and the history information, a prediction of whether the information processing apparatus accesses the storage apparatus in a certain time segment, and control power supply to the storage apparatus based on the prediction.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: October 8, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Atsushi Nukariya, Tsuyoshi Hashimoto
  • Patent number: 10423458
    Abstract: A parallel processing system creates a list when determining a start and an end times of processings for nodes and one or more of the nodes used by the processings, the list indicating an order of executing the processings and a number and positions of nodes used by the processings on coordinate axes, nodes included in the nodes and adjacent to each other in coordinate axis directions on the coordinate axes being coupled to each other, identifies a number of unused nodes on the coordinate axes at a time when the execution of a processing ends before an end time of the processing, and determines, based on the number and the list, a processing, a start time of which is to be advanced, from the processings at a time when the execution of the one of the processings ends before the end time of the one of the processings.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: September 24, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tsutomu Ueno, Tsuyoshi Hashimoto
  • Patent number: 10367886
    Abstract: An information processing apparatus, among a plurality of information processing apparatuses that performs parallel computing processing in a parallel computer system, including a memory and a processor coupled to the memory and configured to execute a process including: calculating a centroid position of the information processing apparatuses based on a data length of data for which subsequent reading or writing from or to a file server is requested by the information processing apparatuses and position information on each of the information processing apparatuses; determining a first information processing apparatus that performs data relay according to the calculated centroid position; and collectively receiving or transmitting, when the determined first information processing apparatus that performs data relay is the information processing apparatus, the data for two or more of the information processing apparatuses.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 30, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Koichiro Harada, Tsuyoshi Hashimoto
  • Patent number: 10331489
    Abstract: Computers are connected via multidimensional mesh or torus connection in a network. In response to a request for executing maintenance processing on computers in the network, an apparatus detects execution-scheduled jobs to be executed after an execution start time of the maintenance processing, based on execution-scheduled start times of jobs to be executed by the computers. The apparatus calculates, for each execution-scheduled job, a characteristic value of an axial length of an execution-scheduled job area in each axial direction of multidimensional axes in the network, where the execution-scheduled job area includes a group of computers to execute the each execution-scheduled job. The apparatus determines a maintenance area in the network on which the maintenance processing is to be executed, based on the characteristic values of the axial lengths of the execution-scheduled job areas, and executes the maintenance processing on computers in the maintenance area.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: June 25, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kazuhiro Matsuyama, Tsuyoshi Hashimoto
  • Patent number: 10268529
    Abstract: A first node determines a second node belonging to the same first group as the first node, and creates a first receive buffer corresponding to the second node in a memory. The first node determines a third and a fourth node belonging to a second group, and creates a second receive buffer corresponding to the third node in the memory, without creating a receive buffer corresponding to the fourth node. The first node uses the first receive buffer to receive messages when communicating with the second node, uses the second receive buffer to receive messages when communicating with the third node, and uses the first receive buffer or the second receive buffer to receive messages when communicating with the fourth node.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: April 23, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Masaaki Fushimi, Tsuyoshi Hashimoto
  • Publication number: 20190028378
    Abstract: An information processing apparatus is configured to receive a request for communication between a first node and a second node included in a parallel calculation system, acquire job execution information relating a job to be executed by the parallel calculation system, generate connected graph information based on first information on the first node, second information on the second node, the job execution information, and topology information indicating a topology of the plurality of nodes, generate, based on the connected graph information, route information indicating a plurality of routes used when the communication between the first node and the second node is executed, specify, based on the route information, a route having the lowest passing cost among the plurality of routes; and specify a node included in the specified route as a relay node based on positions of the plurality of nodes in the specified route.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 24, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Akio Houjyo, Tsuyoshi HASHIMOTO
  • Publication number: 20190018707
    Abstract: A parallel processing control device includes a processor that acquires path status information indicating a communication status of each path connecting between compute nodes. The processor acquires free memory information indicating a status of memory usage in each compute node. The processor determines, when a new job is input, a save target job from among jobs processed by at least a part of the compute nodes. The processor determines, by evaluating data transfer from the respective compute nodes to respective acceptable nodes based on the free memory information and the path status information, destination nodes and a size of data to be transferred between respective pairs of one source node and one destination node. The acceptable nodes are compute nodes having a free memory. The destination nodes are compute nodes to which a part of data of the save target job is to be transferred from the respective source nodes.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 17, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tsutomu Ueno, Tsuyoshi HASHIMOTO
  • Publication number: 20190004857
    Abstract: A parallel processing apparatus includes: a memory; and a processor coupled to the memory, the processor is configured to: acquire a first time and a second time; divide a plurality of nodes into a plurality of groups; generate a plurality of schedule candidates each which assigns time zones corresponding to a length of time used to perform a maintenance operation at one or more nodes included in the plurality of groups in a time period from the first time to the second time to the plurality of groups such that no overlap occurs among the plurality of groups; evaluate the plurality of schedule candidates based on one or more process execution schedules of the one or more nodes in the time period; and output one schedule candidate of the plurality of schedule candidates based on a result of the evaluation.
    Type: Application
    Filed: June 15, 2018
    Publication date: January 3, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Kazuhiro Matsuyama, Tsuyoshi HASHIMOTO
  • Patent number: 10171574
    Abstract: A computer system includes: a reference point determining unit that sets node allocation reference points for the job in association with job attribute information of the job, to node coordinate spaces where the plurality of computation nodes are arranged; and a node set searching unit that searches for a computation node set that is a set of computation nodes satisfying a predetermined condition related to a remote degree that is an estimate index of a communication time from the node allocation reference point in the node coordinate space.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: January 1, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Ryo Kanbayashi, Tsuyoshi Hashimoto