Patents by Inventor Tsuyoshi Mitsuda

Tsuyoshi Mitsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6222403
    Abstract: A slew rate output circuit includes a switching device connected to an output terminal, a driver circuit connected to the switching device for driving the switching device, and a control circuit connected to the driver circuit for controlling the driver circuit in accordance with an input signal so that, in an initial time period after a change in level of the input signal, the average slew rate is higher than that in a subsequent time period.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: April 24, 2001
    Assignee: NEC Corporation
    Inventor: Tsuyoshi Mitsuda
  • Patent number: 5973551
    Abstract: A detection circuit detects an abnormal current which flows through a first output transistor. In this event, the first output transistor is connected to an external power supply via a load resistor. The above detection circuit mainly includes a second transistor, a constant current supply, a third transistor, a fourth transistor, and a comparator circuit. The constant current supply supplies a constant current into the second transistor. Further, the third transistor is connected to the first output transistor and performs an ON-OFF operation in synchronism with the first output transistor. On the other hand, the fourth transistor is connected to the third transistor in serial and performs the ON-OFF operation opposite to the first output transistor. Moreover, the comparator circuit has a first input and a second input.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventor: Tsuyoshi Mitsuda
  • Patent number: 5670867
    Abstract: A current sensing circuit has an output NMOS transistor, connected between an output node and a power supply terminal, for passing a load current of an output load, a pair of sensing NMOS and PMOS transistors connected, in series at a first node, between the output node and the power supply terminal, a control section for supplying a common gate voltage to the transistors, and a voltage detecting section for detecting the potential at the first node. When the output transistor and sensing NMOS transistor are on, the sensing PMOS transistor is off. Accordingly, substantially no current flows through the sensing transistors so that power consumption for sensing operation is reduced. The output transistor is a vertical MOSFET while the sensing transistors are horizontal MOSFET integrated in a semiconductor circuit.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: September 23, 1997
    Assignee: NEC Corporation
    Inventor: Tsuyoshi Mitsuda